mb/lenovo/x201: Add VBOOT support

Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between
RW_A and recovery, which works quite well as a developer mode to test
RW_A with the COREBOOT slot as a fallback.

Change-Id: I9d524988e991457032f63a947606d1b3581de5e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2019-10-10 16:09:52 +02:00 committed by Patrick Georgi
parent f240a3269e
commit e9649218bf
3 changed files with 52 additions and 0 deletions

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@ -23,6 +23,25 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_GBE_REGION
select H8_HAS_BAT_TRESHOLDS_IMPL select H8_HAS_BAT_TRESHOLDS_IMPL
config VBOOT
select VBOOT_VBNV_CMOS
select GBB_FLAG_DISABLE_LID_SHUTDOWN
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select GBB_FLAG_DISABLE_FWMP
select HAS_RECOVERY_MRC_CACHE
config VBOOT_SLOTS_RW_A
default y
config VBOOT_VBNV_OFFSET
hex
default 0x2a
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default lenovo/x201 default lenovo/x201

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@ -78,6 +78,9 @@ entries
#427 5 r 0 unused #427 5 r 0 unused
432 8 h 0 volume 432 8 h 0 volume
# VBOOT
448 128 r 0 vbnv
# coreboot config options: check sums # coreboot config options: check sums
984 16 h 0 check_sum 984 16 h 0 check_sum
#1000 24 r 0 amd_reserved #1000 24 r 0 amd_reserved

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@ -0,0 +1,30 @@
FLASH@0xff800000 0x800000 {
SI_ALL@0x0 0x500000 {
SI_DESC@0x0 0x1000
SI_GBE@0x1000 0x2000
SI_ME@0x3000 0x4ed000
}
SI_BIOS@0x500000 0x300000 {
RW_SECTION_A 0x180000 {
VBLOCK_A 0x10000
FW_MAIN_A(CBFS)
RW_FWID_A 0x40
}
UNIFIED_MRC_CACHE 0x20000 {
RECOVERY_MRC_CACHE 0x10000
RW_MRC_CACHE 0x10000
}
RW_VPD(PRESERVE) 0x1000
SMMSTORE(PRESERVE) 0x40000
WP_RO {
RO_VPD(PRESERVE) 0x1000
RO_SECTION {
FMAP 0x800
RO_FRID 0x40
RO_PADDING 0x7c0
GBB 0x1e000
COREBOOT(CBFS)
}
}
}
}