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soc/intel/meteorlake: Enable `DEFAULT_X2APIC_LATE_WORKAROUND` 

This patch ensures Intel Meteor Lake can enable the X2APIC feature.

While debugging Intel Meteor Lake (MTL) based platforms it seems like
enabling `DEFAULT_X2APIC` runs into a hang while coreboot tries to
bring the application processors (APs) from reset using X2APIC mode.

[INFO ] LAPIC 0x10 switched to X2APIC mode.
...
[DEBUG] Attempting to start 3 APs
[DEBUG] Waiting for 10ms after sending INIT.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[DEBUG] Waiting for SIPI to complete...
[DEBUG] done.
[ERROR] Not all APs checked in: 0/3.
[DEBUG] 0/3 eventually checked in?
[ERROR] MP initialization failure.
[ERROR] MP initialization failure.

Note: The AP bring up flow between XAPIC and X2APIC are the same
except the way to access those LAPIC registers. X2APIC expects to
access all LAPIC registers using MSR (base with 0x800).

The correct flow to enable X2APIC on MTL would be as follows:
1. Let BSP bring all APs in XAPIC mode.

[INFO ]  LAPIC 0x10 in XAPIC mode.
...
[DEBUG]  Attempting to start 3 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x11 in XAPIC mode.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[INFO ]  LAPIC 0x80 in XAPIC mode.

2. Call enable_x2apic() function on all CPUs (BSP and APs)

And at the end of #2 above, all cores will now switch to X2APIC
from XAPIC.

[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device a06a0
[DEBUG]  Clearing out pending MCEs
[INFO ]  LAPIC 0x10 switched to X2APIC mode.
...
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[DEBUG]  CPU: vendor Intel device a06a0
[DEBUG]  Clearing out pending MCEs
[INFO ]  LAPIC 0x11 switched to X2APIC mode.

Note: Intel MTL FSP also follow the same steps for x2APIC enablement
while coreboot selects USE_INTEL_FSP_MP_INIT config instead
MP_SERVICES_PPI_V2.

BUG=b:219061518, b:219053812
TEST=Able to perform coreboot doing AP init with
DEFAULT_X2APIC_LATE_WORKAROUND config enabled without running into
any hang issue.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9c8fad6c46b15b5b08c9cc4ef53f2a6872bd0ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2022-07-09 22:06:45 +00:00 committed by Felix Held
parent f6d725c0d3
commit e96993db69
2 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/meteorlake/Kconfig
View File

@ -15,7 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_INTEL_TME
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select DEFAULT_X2APIC select DEFAULT_X2APIC_LATE_WORKAROUND
select DISPLAY_FSP_VERSION_INFO select DISPLAY_FSP_VERSION_INFO
select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_USB_ACPI select DRIVERS_USB_ACPI

10
src/soc/intel/meteorlake/cpu.c
View File

@ -89,6 +89,14 @@ bool soc_is_nominal_freq_supported(void)
return true; return true;
} }
static void enable_x2apic(void)
{
if (!CONFIG(X2APIC_LATE_WORKAROUND))
return;
enable_lapic_mode(true);
}
/* All CPUs including BSP will run the following function. */ /* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu) void soc_core_init(struct device *cpu)
{ {
@ -98,6 +106,8 @@ void soc_core_init(struct device *cpu)
* every bank. */ * every bank. */
mca_configure(); mca_configure();
enable_x2apic();
enable_lapic_tpr(); enable_lapic_tpr();
/* Configure Enhanced SpeedStep and Thermal Sensors */ /* Configure Enhanced SpeedStep and Thermal Sensors */