mediatek: Share watchdog timer code among similar SOCs
Refactor watchdog timer (WDT) code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27024 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,12 +13,12 @@
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* GNU General Public License for more details.
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*/
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#ifndef SOC_MEDIATEK_MT8173_WDT_H
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#define SOC_MEDIATEK_MT8173_WDT_H
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#ifndef SOC_MEDIATEK_COMMON_WDT_H
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#define SOC_MEDIATEK_COMMON_WDT_H
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#include <stdint.h>
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struct mt8173_wdt_regs {
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struct mtk_wdt_regs {
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u32 wdt_mode;
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u32 wdt_length;
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u32 wdt_restart;
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@ -50,4 +50,4 @@ enum {
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int mtk_wdt_init(void);
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#endif /* SOC_MEDIATEK_MT8173_WDT_H */
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#endif /* SOC_MEDIATEK_COMMON_WDT_H */
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@ -20,14 +20,14 @@
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#include <soc/wdt.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static struct mt8173_wdt_regs *const mt8173_wdt = (void *)RGU_BASE;
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static struct mtk_wdt_regs *const mtk_wdt = (void *)RGU_BASE;
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int mtk_wdt_init(void)
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{
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uint32_t wdt_sta;
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/* Write Mode register will clear status register */
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wdt_sta = read32(&mt8173_wdt->wdt_status);
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wdt_sta = read32(&mtk_wdt->wdt_status);
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printk(BIOS_INFO, "WDT: Last reset was ");
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if (wdt_sta & MTK_WDT_STA_HW_RST) {
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@ -49,7 +49,7 @@ int mtk_wdt_init(void)
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* ENABLE: disable watchdog on initialization.
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* Setting bit EXTEN to enable watchdog output.
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*/
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clrsetbits_le32(&mt8173_wdt->wdt_mode,
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clrsetbits_le32(&mtk_wdt->wdt_mode,
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MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ |
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MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE,
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MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
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@ -59,5 +59,5 @@ int mtk_wdt_init(void)
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void do_hard_reset(void)
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{
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write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
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}
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