soc/intel/apollolake: Enable LPC bus interface
This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14469 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -20,6 +20,7 @@
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#include <soc/bootblock.h>
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#include <soc/cpu.h>
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#include <soc/gpio.h>
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#include <soc/lpc.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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#include <soc/uart.h>
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@ -28,12 +29,36 @@ static const struct pad_config tpm_spi_configs[] = {
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PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
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};
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static const struct pad_config lpc_gpio_configs[] = {
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PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
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};
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static void tpm_enable(void)
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{
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/* Configure gpios */
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gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
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}
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static void early_lpc_enable(void)
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{
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/* Enable requested fixed IO decode ranges */
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pci_write_config16(LPC_DEV, LPC_EN, LPC_EN_MC1 | LPC_EN_KB | LPC_EN_LGAME);
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/* Enable generic IO decode ranges for 0x800-0x9ff */
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/* FIXME: remove range hardcoding and/or calculate based on EC definitions */
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pci_write_config32(LPC_DEV, LPC_GEN1_DEC, ((0xff & ~3 ) << 8) | 0x800 | 1);
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pci_write_config32(LPC_DEV, LPC_GEN2_DEC, ((0xff & ~3 ) << 8) | 0x900 | 1);
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/* GPIO pins need to be configured to specific native function */
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gpio_configure_pads(lpc_gpio_configs, ARRAY_SIZE(lpc_gpio_configs));
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}
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void asmlinkage bootblock_c_entry(void)
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{
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device_t dev = NB_DEV_ROOT;
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@ -59,4 +84,8 @@ void bootblock_soc_early_init(void)
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if (IS_ENABLED(CONFIG_LPC_TPM))
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tpm_enable();
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC))
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early_lpc_enable();
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}
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@ -32,6 +32,15 @@ struct soc_intel_apollolake_config {
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uint8_t pcie_rp3_clkreq_pin;
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uint8_t pcie_rp4_clkreq_pin;
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uint8_t pcie_rp5_clkreq_pin;
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* LPC port ranges */
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uint16_t lpc_dec;
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};
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#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
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@ -0,0 +1,40 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_APOLLOLAKE_LPC_H
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#define _SOC_APOLLOLAKE_LPC_H
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/* PCI Configuration Space (D31:F0): LPC */
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#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define LPC_EN_COMA (1 << 0) /* COM port A */
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#define LPC_EN_COMB (1 << 1) /* COM port B */
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#define LPC_EN_PARP (1 << 2) /* Parallel port */
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#define LPC_EN_FLP (1 << 3) /* Floppy */
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#define LPC_EN_LGAME (1 << 8) /* Low Gameport, 0x200-0x207 */
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#define LPC_EN_HGAME (1 << 9) /* High Gameport, 0x208-0x20f */
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#define LPC_EN_KB (1 << 10) /* Keyboard, 0x60, 0x64 */
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#define LPC_EN_MC1 (1 << 11) /* Microcontroller #1, 0x62, 0x66 */
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#define LPC_EN_MC2 (1 << 13) /* Microcontroller #2, 0x4e, 0x4f */
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#define LPC_EN_SIO (1 << 12) /* Super IO, 0x2e, 0x2f */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8C /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#endif //_SOC_APOLLOLAKE_LPC_H
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@ -48,8 +48,11 @@
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#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
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#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
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#define LPC_SLOT 0x1f
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#define P2SB_DEV PCI_DEV(0, 0xd, 0)
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#define PMC_DEV PCI_DEV(0, 0xd, 1)
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#define SPI_DEV PCI_DEV(0, 0xd, 2)
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#define LPC_DEV PCI_DEV(0, LPC_SLOT, 0)
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#endif
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2015-2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -20,6 +20,46 @@
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#include <device/pci_ids.h>
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#include <soc/acpi.h>
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#include <soc/pci_ids.h>
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#include <reg_script.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/lpc.h>
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#include "chip.h"
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static const struct reg_script lpc_serirq_enable[] = {
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/* Setup SERIRQ, enable continuous mode */
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REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
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#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
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REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
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#endif
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REG_SCRIPT_END
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};
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static void enable_lpc_decode(struct device *lpc)
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{
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const struct soc_intel_apollolake_config *config;
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if (!lpc || !lpc->chip_info)
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return;
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config = lpc->chip_info;
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/* Enable requested fixed IO decode ranges */
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pci_write_config16(lpc, LPC_EN, config->lpc_dec);
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/* Enable generic IO decode ranges */
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pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec);
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}
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static void lpc_init(struct device *dev)
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{
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enable_lpc_decode(dev);
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reg_script_run_on_dev(dev, lpc_serirq_enable);
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}
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static void soc_lpc_add_io_resources(device_t dev)
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{
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@ -46,6 +86,7 @@ static struct device_operations device_ops = {
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.write_acpi_tables = southbridge_write_acpi_tables,
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.init = &lpc_init
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};
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static const struct pci_driver soc_lpc __pci_driver = {
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