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mb/google/sarien: Set PL1 and PL2 values 

Set PL1 and PL2 values to 25W and 51W respectively for
processor power limits control.

BRANCH=None
BUG=b:122343940
TEST=Built and tested on Arcada system

Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2019-01-14 16:38:25 +05:30 committed by Patrick Georgi
parent 0dbce4042f
commit e97e90959c
4 changed files with 8 additions and 4 deletions
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2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -33,6 +33,8 @@ chip soc/intel/cannonlake
register "dptf_enable" = "1" register "dptf_enable" = "1"
register "dmipwroptimize" = "1" register "dmipwroptimize" = "1"
register "satapwroptimize" = "1" register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port

4
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
View File

@ -43,7 +43,7 @@ Name (MPPC, Package ()
Package () { /* Power Limit 1 */ Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
3000, /* PowerLimitMinimum */ 3000, /* PowerLimitMinimum */
15000, /* PowerLimitMaximum */ 25000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */
100 /* StepSize */ 100 /* StepSize */
@ -51,7 +51,7 @@ Name (MPPC, Package ()
Package () { /* Power Limit 2 */ Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
15000, /* PowerLimitMinimum */ 15000, /* PowerLimitMinimum */
44000, /* PowerLimitMaximum */ 51000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */
100 /* StepSize */ 100 /* StepSize */

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -42,6 +42,8 @@ chip soc/intel/cannonlake
register "SlowSlewRateForGt" = "2" register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2" register "SlowSlewRateForSa" = "2"
register "SlowSlewRateForFivr" = "2" register "SlowSlewRateForFivr" = "2"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port

4
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
View File

@ -43,7 +43,7 @@ Name (MPPC, Package ()
Package () { /* Power Limit 1 */ Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
3000, /* PowerLimitMinimum */ 3000, /* PowerLimitMinimum */
15000, /* PowerLimitMaximum */ 25000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */
100 /* StepSize */ 100 /* StepSize */
@ -51,7 +51,7 @@ Name (MPPC, Package ()
Package () { /* Power Limit 2 */ Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
15000, /* PowerLimitMinimum */ 15000, /* PowerLimitMinimum */
44000, /* PowerLimitMaximum */ 51000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */ 28000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */ 32000, /* TimeWindowMaximum */
100 /* StepSize */ 100 /* StepSize */