Clean up some more comments and white space in model_gx2/cpureginit.c.
This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Uwe Hermann
parent
5beac7f996
commit
e98db798c9
1 changed files with 55 additions and 74 deletions
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@ -1,134 +1,120 @@
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/* ***************************************************************************/
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/* * cpuRegInit*/
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/* ***************************************************************************/
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/* cpuRegInit */
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void cpuRegInit (void)
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{
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int msrnum;
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msr_t msr;
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/* Turn on BTM for early debug based on setup. */
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/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
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/*
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* The following is only for diagnostics mode; do not use for OLPC
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*/
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/* Turn on BTM for early debug based on setup. */
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/* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */
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/* The following is only for diagnostics mode; do not use for OLPC */
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if (0) {
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/* Set Diagnostic Mode */
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/* Set Diagnostic Mode */
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msrnum = CPU_GLD_MSR_DIAG;
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msr.hi = 0;
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msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
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wrmsr(msrnum, msr);
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/* Set up GLCP to grab BTM data.*/
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msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
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/* Set up GLCP to grab BTM data. */
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msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR */
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msr.hi = 0x0;
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
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/* ;Turn off debug clock*/
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/* Turn off debug clock */
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x00; /* No clock*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set debug clock to CPU*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x01; /* CPU CLOCK*/
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/* Set debug clock to CPU */
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msrnum = 0x04C000016; /* DBG_CLK_CTL */
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msr.lo = 0x01; /* CPU CLOCK */
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set fifo ctl to BTM bits wide*/
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msrnum = 0x04C00005E; /* FIFO_CTL*/
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
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wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
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/* Bit [19] sets it up in slow data mode.*/
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/* Set fifo ctl to BTM bits wide */
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msrnum = 0x04C00005E; /* FIFO_CTL */
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */
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wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */
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/* Bit [19] sets it up in slow data mode. */
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/* ;enable fifo loading - BTM sizing will constrain*/
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/* ; only valid BTM packets to load - this action should always be on*/
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
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msr.hi = 0x000000000; /* */
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wrmsr(msrnum, msr);
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/* ;start storing diag data in the fifo*/
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msrnum = 0x04C00005F; /* DIAG CTL*/
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msr.lo = 0x080000000; /* enable actions*/
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/* enable fifo loading - BTM sizing will constrain */
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/* only valid BTM packets to load - this action should always be on */
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up delay on data lines, so that the hold time*/
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/* is 1 ns.*/
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msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
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/* start storing diag data in the fifo */
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msrnum = 0x04C00005F; /* DIAG CTL */
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msr.lo = 0x080000000; /* enable actions */
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins.*/
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/* Set up delay on data lines, so that the hold time */
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/* is 1 ns. */
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msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS */
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins. */
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msrnum = DF_GLD_MSR_MASTER_CONF;
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msr.lo = 0x0220;
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msr.hi = 0;
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wrmsr(msrnum, msr);
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msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
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msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */
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msr.hi = 0x0;
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
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wrmsr(msrnum, msr);
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/* end of code for BTM */
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}
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/* Enable Suspend on Halt*/
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/* Enable Suspend on Halt */
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msrnum = CPU_XC_CONFIG;
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msr = rdmsr(msrnum);
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msr.lo |= XC_CONFIG_SUSP_ON_HLT;
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wrmsr(msrnum, msr);
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/* ENable SUSP and allow TSC to run in Suspend */
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/* to keep speed detection happy*/
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/* ENable SUSP and allow TSC to run in Suspend */
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/* to keep speed detection happy */
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msrnum = CPU_BC_CONF_0;
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msr = rdmsr(msrnum);
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msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
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wrmsr(msrnum, msr);
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/* Setup throttling to proper mode if it is ever enabled.*/
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/* Setup throttling to proper mode if it is ever enabled. */
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msrnum = 0x04C00001E;
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msr.hi = 0x000000000;
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msr.lo = 0x00000603C;
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wrmsr(msrnum, msr);
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/* Only do this if we are building for 5535*/
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/* */
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/* FooGlue Setup*/
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/* */
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/* Only do this if we are building for 5535 */
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/* FooGlue Setup */
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#if 1
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/* Enable CIS mode B in FooGlue*/
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/* Enable CIS mode B in FooGlue */
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msrnum = MSR_FG + 0x10;
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msr = rdmsr(msrnum);
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msr.lo &= ~3;
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msr.lo |= 2; /* ModeB*/
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msr.lo |= 2; /* ModeB */
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wrmsr(msrnum, msr);
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#endif
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/* */
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/* Disable DOT PLL. Graphics init will enable it if needed.*/
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/* */
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/* Disable DOT PLL. Graphics init will enable it if needed. */
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msrnum = GLCP_DOTPLL;
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msr = rdmsr(msrnum);
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msr.lo |= DOTPPL_LOWER_PD_SET;
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wrmsr(msrnum, msr);
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/* */
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/* Enable RSDC*/
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/* */
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/* Enable RSDC */
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msrnum = 0x1301 ;
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msr = rdmsr(msrnum);
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msr.lo |= 0x08;
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wrmsr(msrnum, msr);
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/* */
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/* Enable BTB*/
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/* */
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/* I hate to put this check here but it doesn't really work in cpubug.asm*/
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/* Enable BTB */
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/* I hate to put this check here but it doesn't really work in cpubug.asm */
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msrnum = MSR_GLCP+0x17;
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msr = rdmsr(msrnum);
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if (msr.lo >= CPU_REV_2_1){
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@ -138,10 +124,8 @@ void cpuRegInit (void)
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wrmsr(msrnum, msr);
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}
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/* */
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/* FPU impercise exceptions bit*/
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/* */
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/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
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/* FPU impercise exceptions bit */
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/* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */
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{
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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@ -150,16 +134,13 @@ void cpuRegInit (void)
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}
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#if 0
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/* */
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/* Cache Overides*/
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/* */
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/* Cache Overides */
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/* This code disables the data cache. Don't execute this
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* unless you're testing something.
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*/
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/* Allow NVRam to override DM Setup*/
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/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
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/* Allow NVRam to override DM Setup */
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/* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */
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{
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
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@ -168,8 +149,8 @@ void cpuRegInit (void)
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/* This code disables the instruction cache. Don't execute
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* this unless you're testing something.
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*/
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/* Allow NVRam to override IM Setup*/
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/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
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/* Allow NVRam to override IM Setup */
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/* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */
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{
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msrnum = CPU_IM_CONFIG;
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msr = rdmsr(msrnum);
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