mb/asrock/g41c-gs: Add the revision 1 variant
Both g41c-gs and g41c-s can be supported by the same code since the only difference is ethernet NIC. What is tested: TODO: components How tested: TODO: payload + OS Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Felix Held
parent
61c3b593e4
commit
e98f305abd
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@ -14,7 +14,7 @@
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# GNU General Public License for more details.
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#
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if BOARD_ASROCK_G41C_GS_R2_0
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if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -22,7 +22,8 @@ config BOARD_SPECIFIC_OPTIONS
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select CPU_INTEL_SOCKET_LGA775
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select NORTHBRIDGE_INTEL_X4X
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select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_NUVOTON_NCT6776
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select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
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select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_1024
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select PCIEXP_ASPM
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@ -41,10 +42,20 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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string
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default "G41C-GS R2.0"
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default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
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default "G41C-GS" if BOARD_ASROCK_G41C_GS
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config DEVICETREE
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string
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default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
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default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
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config MAX_CPUS
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int
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default 4
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# Override the default variant behavior, since the data.vbt is the same
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config INTEL_GMA_VBT_FILE
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default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
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endif # BOARD_ASROCK_G41C_GS_R2_0
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@ -1,2 +1,5 @@
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config BOARD_ASROCK_G41C_GS_R2_0
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bool "G41C-GS R2.0"
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config BOARD_ASROCK_G41C_GS
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bool "G41C-GS / G41C-S"
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@ -57,6 +57,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio28 = GPIO_DIR_INPUT,
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};
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#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio10 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_LOW,
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@ -67,6 +68,18 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio25 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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};
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#else /* BOARD_ASROCK_G41C_GS */
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio10 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio16 = GPIO_LEVEL_HIGH,
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.gpio18 = GPIO_LEVEL_LOW,
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.gpio20 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_HIGH,
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.gpio25 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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};
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#endif
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio0 = GPIO_INVERT,
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@ -22,6 +22,8 @@
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#include <cpu/x86/bist.h>
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#include <cpu/intel/romstage.h>
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#include <superio/nuvoton/nct6776/nct6776.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <lib.h>
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#include <arch/stages.h>
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@ -30,7 +32,8 @@
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#include <device/pnp_def.h>
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#include <timestamp.h>
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#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
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#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
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#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
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#define SUPERIO_DEV PNP_DEV(0x2e, 0)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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@ -44,15 +47,19 @@ static void mb_lpc_setup(void)
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setup_pch_gpios(&mainboard_gpio_map);
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/* Set GPIOs on superio, enable UART */
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nuvoton_pnp_enter_conf_state(SERIAL_DEV);
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pnp_set_logical_device(SERIAL_DEV);
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if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) {
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nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
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pnp_set_logical_device(SERIAL_DEV_R2);
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pnp_write_config(SERIAL_DEV, 0x1c, 0x80);
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pnp_write_config(SERIAL_DEV, 0x27, 0x80);
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pnp_write_config(SERIAL_DEV, 0x2a, 0x60);
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nuvoton_pnp_exit_conf_state(SERIAL_DEV);
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pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
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pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
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pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
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nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
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nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
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} else { /* BOARD_ASROCK_G41C_GS */
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winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
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}
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/* IRQ routing */
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RCBA16(D31IR) = 0x0132;
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RCBA16(D29IR) = 0x0237;
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@ -91,7 +98,6 @@ void mainboard_romstage_entry(unsigned long bist)
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/* Set southbridge and Super I/O GPIOs. */
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ich7_enable_lpc();
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mb_lpc_setup();
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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@ -0,0 +1,138 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
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end
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end
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device domain 0 on # PCI domain
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subsystemid 0x1458 0x5000 inherit
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device pci 0.0 on # Host Bridge
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subsystemid 0x1849 0x2e30
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end
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device pci 1.0 on end # PEG
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device pci 2.0 on # Integrated graphics controller
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subsystemid 0x1849 0x2e32
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end
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device pci 3.0 off end # ME
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device pci 3.1 off end # ME
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chip southbridge/intel/i82801gx # Southbridge
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x0b"
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register "ide_enable_primary" = "0x1"
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register "gpe0_en" = "0x440"
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device pci 1b.0 on # Audio
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subsystemid 0x1849 0x3662
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end
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device pci 1c.0 on end # PCIe 1
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device pci 1c.1 on end # PCIe 2
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1c.4 off end # PCIe 5
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device pci 1c.5 off end # PCIe 6
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device pci 1d.0 on # USB
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subsystemid 0x1849 0x27c8
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end
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device pci 1d.1 on # USB
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subsystemid 0x1849 0x27c9
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end
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device pci 1d.2 on # USB
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subsystemid 0x1849 0x27ca
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end
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device pci 1d.3 on # USB
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subsystemid 0x1849 0x27cb
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end
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device pci 1d.7 on # USB
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subsystemid 0x1849 0x27cc
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end
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device pci 1e.0 on end # PCI bridge
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device pci 1e.2 off end # AC'97 Audio
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device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # ISA bridge
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subsystemid 0x1849 0x27b8
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chip superio/winbond/w83627dhg
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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# global
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irq 0x28 = 0x70
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irq 0x2c = 0xd2
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# parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off end # COM2
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device pnp 2e.5 on # Keyboard & MOUSE
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 0x0C
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end
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device pnp 2e.6 off end # SPI
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device pnp 2e.7 off end # GPIO6
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device pnp 2e.8 off end # WDT0#, PLED
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device pnp 2e.9 off end # GPIO2
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device pnp 2e.109 off end # GPIO3
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device pnp 2e.209 on # GPIO4
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irq 0xf4 = 0x73
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end
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device pnp 2e.309 off end # GPIO5
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device pnp 2e.a on # ACPI
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irq 0xe4 = 0x10 # Power dram during s3
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end
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device pnp 2e.b on # HWM, front pannel LED
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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device pnp 2e.c off end # PECI, SST
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end
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end
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device pci 1f.1 on # PATA/IDE
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subsystemid 0x1849 0x27df
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end
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device pci 1f.2 on # SATA
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subsystemid 0x1849 0x27c0
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end
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device pci 1f.3 on # SMbus
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subsystemid 0x1849 0x27da
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chip drivers/i2c/ck505 # W83115RG-965
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# set SATA to fixed 100Mhz refclk
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register "mask" = "{ 0x02 }"
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register "regs" = "{ 0x02 }"
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device i2c 69 on end
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end
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end
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end
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end
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end
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