Remove VIA CX700 northbridge support
Change-Id: Id46e3d40393598f6b03ae4fd3186182635f072ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
ec953bc2f9
commit
e99f0390b9
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@ -1,55 +0,0 @@
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config NORTHBRIDGE_VIA_CX700
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bool
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select HAVE_DEBUG_SMBUS
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select HAVE_HARD_RESET
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select IOAPIC
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select SMP
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select LATE_CBMEM_INIT
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# TODO: What should be the per-chipset default value here?
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choice
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prompt "Onboard graphics"
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default CX700_VIDEO_MB_32MB
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depends on NORTHBRIDGE_VIA_CX700
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# TODO: Setting the amount of gfx memory is not yet supported in the source code.
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config CX700_VIDEO_MB_OFF
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bool "Disabled, 0KB"
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config CX700_VIDEO_MB_8MB
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bool "Enabled, 8MB"
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config CX700_VIDEO_MB_16MB
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bool "Enabled, 16MB"
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config CX700_VIDEO_MB_32MB
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bool "Enabled, 32MB"
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config CX700_VIDEO_MB_64MB
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bool "Enabled, 64MB"
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config CX700_VIDEO_MB_128MB
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bool "Enabled, 128MB"
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endchoice
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if NORTHBRIDGE_VIA_CX700
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config VIDEO_MB
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int
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default 0 if CX700_VIDEO_MB_OFF
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default 8 if CX700_VIDEO_MB_8MB
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default 16 if CX700_VIDEO_MB_16MB
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default 32 if CX700_VIDEO_MB_32MB
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default 64 if CX700_VIDEO_MB_64MB
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default 128 if CX700_VIDEO_MB_128MB
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config HPET_ADDRESS_OVERRIDE
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def_bool y
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config HPET_ADDRESS
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hex
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default 0xfe800000
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config HPET_MIN_TICKS
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hex
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default 0x90
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endif
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@ -1,26 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y)
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ramstage-y += reset.c
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ramstage-y += northbridge.c
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ramstage-y += agp.c
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ramstage-y += lpc.c
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ramstage-y += sata.c
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ramstage-y += vga.c
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endif
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@ -1,83 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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/* This is the AGP 3.0 "bridge" @ Bus 0 Device 1 Func 0 */
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static void agp_bridge_init(struct device *dev)
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{
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struct device *north_dev;
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u8 reg8;
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north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
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pci_write_config8(north_dev, 0xa0, 0x1); // Enable CPU Direct Access Frame Buffer
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pci_write_config8(north_dev, 0xa2, 0x4a);
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reg8 = pci_read_config8(north_dev, 0xc0);
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reg8 |= 0x1;
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pci_write_config8(north_dev, 0xc0, reg8);
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/*
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* Since Internal Graphic already set to AGP3.0 compatible in its Capability Pointer
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* We must set RAGP8X=1 B0D0F0 Rx84[3]=1 from backdoor register B0D0F0 RxB5[1:0]=11b
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*/
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north_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x0324, 0);
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reg8 = pci_read_config8(north_dev, 0xb5);
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reg8 |= 0x3;
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pci_write_config8(north_dev, 0xb5, reg8);
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pci_write_config8(north_dev, 0x94, 0x20);
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pci_write_config8(north_dev, 0x13, 0xd0);
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pci_write_config16(dev, 0x4, 0x0007);
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pci_write_config8(dev, 0x19, 0x01);
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pci_write_config8(dev, 0x1a, 0x01);
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pci_write_config8(dev, 0x1c, 0xe0);
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pci_write_config8(dev, 0x1d, 0xe0);
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pci_write_config16(dev, 0x1e, 0xa220);
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pci_write_config16(dev, 0x20, 0xdd00);
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pci_write_config16(dev, 0x22, 0xdef0);
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pci_write_config16(dev, 0x24, 0xa000);
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pci_write_config16(dev, 0x26, 0xbff0);
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pci_write_config8(dev, 0x3e, 0x0c);
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pci_write_config8(dev, 0x40, 0x8b);
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pci_write_config8(dev, 0x41, 0x43);
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pci_write_config8(dev, 0x42, 0x62);
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pci_write_config8(dev, 0x43, 0x44);
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pci_write_config8(dev, 0x44, 0x34);
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}
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static struct device_operations agp_bridge_operations = {
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.read_resources = DEVICE_NOOP,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = agp_bridge_init,
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.scan_bus = pci_scan_bridge,
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};
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static const struct pci_driver agp_bridge_driver __pci_driver = {
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.ops = &agp_bridge_operations,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = 0xb198,
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};
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@ -1,98 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Enable the serial devices on the VIA CX700
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*/
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#include <arch/io.h>
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static void cx700_writepnpaddr(u8 val)
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{
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outb(val, 0x2e);
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outb(val, 0xeb);
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}
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static void cx700_writepnpdata(u8 val)
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{
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outb(val, 0x2f);
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outb(val, 0xeb);
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}
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static void cx700_writesiobyte(u16 reg, u8 val)
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{
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outb(val, reg);
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}
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static void cx700_writesioword(u16 reg, u16 val)
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{
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outw(val, reg);
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}
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static void enable_cx700_serial(void)
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{
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post_code(0x06);
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// WTH?
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outb(0x03, 0x22);
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// Set UART1 I/O Base Address
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pci_write_config8(PCI_DEV(0, 17, 0), 0xb4, 0x7e);
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// UART1 Enable
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pci_write_config8(PCI_DEV(0, 17, 0), 0xb0, 0x10);
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// turn on pnp
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cx700_writepnpaddr(0x87);
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cx700_writepnpaddr(0x87);
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// now go ahead and set up com1.
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// set address
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cx700_writepnpaddr(0x7);
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cx700_writepnpdata(0x2);
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// enable serial out
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cx700_writepnpaddr(0x30);
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cx700_writepnpdata(0x1);
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// serial port 1 base address (FEh)
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cx700_writepnpaddr(0x60);
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cx700_writepnpdata(0xfe);
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// serial port 1 IRQ (04h)
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cx700_writepnpaddr(0x70);
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cx700_writepnpdata(0x4);
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// serial port 1 control
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cx700_writepnpaddr(0xf0);
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cx700_writepnpdata(0x2);
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// turn of pnp
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cx700_writepnpaddr(0xaa);
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// XXX This part should be fully taken care of by
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// src/lib/uart8250.c:uart_init
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// set up reg to set baud rate.
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cx700_writesiobyte(0x3fb, 0x80);
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// Set 115 kb
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cx700_writesioword(0x3f8, 1);
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// Set 9.6 kb
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// cx700_writesioword(0x3f8, 12)
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// now set no parity, one stop, 8 bits
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cx700_writesiobyte(0x3fb, 3);
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// now turn on RTS, DRT
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cx700_writesiobyte(0x3fc, 3);
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// Enable interrupts
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cx700_writesiobyte(0x3f9, 0xf);
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// should be done. Dump a char for fun.
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cx700_writesiobyte(0x3f8, 48);
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post_code(0x07);
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}
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@ -1,240 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// other bioses use this, too:
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#define SMBUS_IO_BASE 0x0500
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#define SMBHSTSTAT SMBUS_IO_BASE + 0x0
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#define SMBSLVSTAT SMBUS_IO_BASE + 0x1
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#define SMBHSTCTL SMBUS_IO_BASE + 0x2
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#define SMBHSTCMD SMBUS_IO_BASE + 0x3
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#define SMBXMITADD SMBUS_IO_BASE + 0x4
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#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
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#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
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#define SMBBLKDAT SMBUS_IO_BASE + 0x7
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#define SMBSLVCTL SMBUS_IO_BASE + 0x8
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#define SMBTRNSADD SMBUS_IO_BASE + 0x9
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#define SMBSLVDATA SMBUS_IO_BASE + 0xa
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#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
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#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
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/* Define register settings */
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#define HOST_RESET 0xff
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#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
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#define SMBUS_TIMEOUT (100*1000*10)
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#define I2C_TRANS_CMD 0x40
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#define CLOCK_SLAVE_ADDRESS 0x69
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#define SMBUS_DELAY() outb(0x80, 0x80)
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/* Internal functions */
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#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
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static void smbus_print_error(unsigned char host_status_register, int loops)
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{
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/* Check if there actually was an error */
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if (host_status_register == 0x00 || host_status_register == 0x40 ||
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host_status_register == 0x42)
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return;
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printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
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if (loops >= SMBUS_TIMEOUT) {
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printk(BIOS_ERR, "SMBus Timout\n");
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}
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if (host_status_register & (1 << 4)) {
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printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
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}
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if (host_status_register & (1 << 3)) {
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printk(BIOS_ERR, "Bus Error\n");
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}
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if (host_status_register & (1 << 2)) {
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printk(BIOS_ERR, "Device Error\n");
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}
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if (host_status_register & (1 << 1)) {
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/* This isn't a real error... */
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printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
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}
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if (host_status_register & (1 << 0)) {
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printk(BIOS_ERR, "Host Busy\n");
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}
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}
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#endif
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static void smbus_wait_until_ready(void)
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{
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int loops;
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loops = 0;
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/* Yes, this is a mess, but it's the easiest way to do it */
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while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
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SMBUS_DELAY();
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++loops;
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}
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#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
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/* Some systems seem to have a flakey SMBus. No need to spew a lot of
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* errors on those, once we know that SMBus access is principally
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* working.
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*/
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smbus_print_error(inb(SMBHSTSTAT), loops);
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#endif
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}
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static void smbus_reset(void)
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{
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outb(HOST_RESET, SMBHSTSTAT);
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}
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/* Public functions */
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static void set_ics_data(unsigned char dev, int data, char len)
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{
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smbus_reset();
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/* clear host data port */
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outb(0x00, SMBHSTDAT0);
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SMBUS_DELAY();
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smbus_wait_until_ready();
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/* read to reset block transfer counter */
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inb(SMBHSTCTL);
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/* fill blocktransfer array */
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if (dev == 0xd2) {
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outb(0x0d, SMBBLKDAT);
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outb(0x00, SMBBLKDAT);
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outb(0x3f, SMBBLKDAT);
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outb(0xcd, SMBBLKDAT);
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outb(0x7f, SMBBLKDAT);
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outb(0xbf, SMBBLKDAT);
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outb(0x1a, SMBBLKDAT);
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outb(0x2a, SMBBLKDAT);
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outb(0x01, SMBBLKDAT);
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outb(0x0f, SMBBLKDAT);
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outb(0x0b, SMBBLKDAT);
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outb(0x80, SMBBLKDAT);
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outb(0x8d, SMBBLKDAT);
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outb(0x9b, SMBBLKDAT);
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} else {
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outb(0x08, SMBBLKDAT);
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outb(0xff, SMBBLKDAT);
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outb(0x3f, SMBBLKDAT);
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outb(0x00, SMBBLKDAT);
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outb(0x00, SMBBLKDAT);
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outb(0xff, SMBBLKDAT);
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outb(0xff, SMBBLKDAT);
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outb(0xff, SMBBLKDAT);
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outb(0xff, SMBBLKDAT);
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}
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outb(dev, SMBXMITADD);
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outb(0, SMBHSTCMD);
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outb(len, SMBHSTDAT0);
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outb(0x74, SMBHSTCTL);
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SMBUS_DELAY();
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smbus_wait_until_ready();
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smbus_reset();
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}
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static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm,
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unsigned int offset)
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{
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unsigned int val, addr;
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smbus_reset();
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/* clear host data port */
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outb(0x00, SMBHSTDAT0);
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SMBUS_DELAY();
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smbus_wait_until_ready();
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/* Fetch the SMBus address of the SPD ROM from
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* the ctrl struct in romstage.c in case they are at
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* non-standard positions.
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* SMBus Address shifted by 1
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*/
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addr = (ctrl->channel0[dimm]) << 1;
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outb(addr | 0x1, SMBXMITADD);
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outb(offset, SMBHSTCMD);
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outb(0x48, SMBHSTCTL);
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SMBUS_DELAY();
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smbus_wait_until_ready();
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val = inb(SMBHSTDAT0);
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smbus_reset();
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return val;
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}
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static void enable_smbus(void)
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{
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pci_devfn_t dev;
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/* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location,
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* no need to probe.
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*/
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dev = PCI_DEV(0, 17, 0);
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/* SMBus Clock Select: Divider fof 14.318MHz */
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pci_write_config8(dev, 0x94, 0x20);
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|
||||
/* SMBus I/O Base, enable SMBus */
|
||||
pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
|
||||
|
||||
/* SMBus Clock from 128K Source, Enable SMBus Host Controller */
|
||||
pci_write_config8(dev, 0xd2, 0x05);
|
||||
|
||||
/* Enable I/O decoding */
|
||||
pci_write_config16(dev, 0x04, 0x0003);
|
||||
|
||||
/* Setup clock chips */
|
||||
set_ics_data(0xd2, 0, 14);
|
||||
set_ics_data(0xd4, 0, 9);
|
||||
}
|
||||
|
||||
/* Debugging Function */
|
||||
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
|
||||
static void dump_spd_data(const struct mem_controller *ctrl)
|
||||
{
|
||||
int dimm, offset, regs;
|
||||
unsigned int val;
|
||||
|
||||
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
|
||||
printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
|
||||
|
||||
val = get_spd_data(ctrl, dimm, 0);
|
||||
if (val == 0xff) {
|
||||
regs = 256;
|
||||
} else if (val == 0x80) {
|
||||
regs = 128;
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "No DIMM present\n");
|
||||
regs = 0;
|
||||
}
|
||||
for (offset = 0; offset < regs; offset++) {
|
||||
printk(BIOS_DEBUG, " Offset %02x = 0x%02x\n",
|
||||
offset, get_spd_data(ctrl, dimm, offset));
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define dump_spd_data(ctrl)
|
||||
#endif
|
||||
|
|
@ -1,301 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <pc80/i8259.h>
|
||||
#include <pc80/keyboard.h>
|
||||
#include <pc80/isa-dma.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#define ACPI_IO_BASE 0x400
|
||||
|
||||
static const unsigned char pci_irqs[4] = { 11, 11, 10, 10 };
|
||||
|
||||
static const unsigned char usb_pins[4] = { 'A', 'B', 'C', 'D' };
|
||||
static const unsigned char vga_pins[4] = { 'A', 'B', 'C', 'D' };
|
||||
static const unsigned char slot_pins[4] = { 'B', 'C', 'D', 'A' };
|
||||
static const unsigned char ac97_pins[4] = { 'B', 'C', 'D', 'A' };
|
||||
|
||||
static unsigned char *pin_to_irq(const unsigned char *pin)
|
||||
{
|
||||
static unsigned char irqs[4];
|
||||
int i;
|
||||
for (i = 0; i < 4; i++)
|
||||
irqs[i] = pci_irqs[pin[i] - 'A'];
|
||||
|
||||
return irqs;
|
||||
}
|
||||
|
||||
static void pci_routing_fixup(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "%s: device is %p\n", __FUNCTION__, dev);
|
||||
|
||||
/* set up PCI IRQ routing */
|
||||
pci_write_config8(dev, 0x55, pci_irqs[0] << 4);
|
||||
pci_write_config8(dev, 0x56, pci_irqs[1] | (pci_irqs[2] << 4));
|
||||
pci_write_config8(dev, 0x57, pci_irqs[3] << 4);
|
||||
|
||||
/* Assigning IRQs */
|
||||
printk(BIOS_DEBUG, "Setting up USB interrupts.\n");
|
||||
pci_assign_irqs(0, 0x10, pin_to_irq(usb_pins));
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up VGA interrupts.\n");
|
||||
pci_assign_irqs(1, 0x00, pin_to_irq(vga_pins));
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up PCI slot interrupts.\n");
|
||||
pci_assign_irqs(2, 0x04, pin_to_irq(slot_pins));
|
||||
// more?
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up AC97 interrupts.\n");
|
||||
pci_assign_irqs(0x80, 0x1, pin_to_irq(ac97_pins));
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the power management capabilities directly into ACPI mode. This
|
||||
* avoids having to handle any System Management Interrupts (SMI's) which I
|
||||
* can't figure out how to do !!!!
|
||||
*/
|
||||
|
||||
static void setup_pm(struct device *dev)
|
||||
{
|
||||
/* Debounce LID and PWRBTN# Inputs for 16ms. */
|
||||
pci_write_config8(dev, 0x80, 0x20);
|
||||
|
||||
/* Set ACPI base address to IO ACPI_IO_BASE */
|
||||
pci_write_config16(dev, 0x88, ACPI_IO_BASE | 1);
|
||||
|
||||
/* set ACPI irq to 9 */
|
||||
pci_write_config8(dev, 0x82, 0x49);
|
||||
|
||||
/* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */
|
||||
pci_write_config16(dev, 0x84, 0x609a);
|
||||
|
||||
/* SMI output level to low, 7.5us throttle clock */
|
||||
pci_write_config8(dev, 0x8d, 0x18);
|
||||
|
||||
/* GP Timer Control 1s */
|
||||
pci_write_config8(dev, 0x93, 0x88);
|
||||
|
||||
/* Power Well */
|
||||
pci_write_config8(dev, 0x94, 0x20); // 0x20??
|
||||
|
||||
/* 7 = stp to sust delay 1msec
|
||||
* 6 = SUSST# Deasserted Before PWRGD for STD
|
||||
*/
|
||||
pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
|
||||
|
||||
/* Disable GP2 & GP3 Timer */
|
||||
pci_write_config8(dev, 0x98, 0);
|
||||
|
||||
/* GP2 Timer Counter */
|
||||
pci_write_config8(dev, 0x99, 0xfb);
|
||||
/* GP3 Timer Counter */
|
||||
|
||||
/* Multi Function Select 1 */
|
||||
pci_write_config8(dev, 0xe4, 0x00);
|
||||
|
||||
/* Multi Function Select 2 */
|
||||
pci_write_config8(dev, 0xe5, 0x41); //??
|
||||
|
||||
/* Enable ACPI access (and setup like award) */
|
||||
pci_write_config8(dev, 0x81, 0x84);
|
||||
|
||||
/* Clear status events. */
|
||||
outw(0xffff, ACPI_IO_BASE + 0x00);
|
||||
outw(0xffff, ACPI_IO_BASE + 0x20);
|
||||
outw(0xffff, ACPI_IO_BASE + 0x28);
|
||||
outl(0xffffffff, ACPI_IO_BASE + 0x30);
|
||||
|
||||
/* Disable SCI on GPIO. */
|
||||
outw(0x0, ACPI_IO_BASE + 0x22);
|
||||
|
||||
/* Disable SMI on GPIO. */
|
||||
outw(0x0, ACPI_IO_BASE + 0x24);
|
||||
|
||||
/* Disable all global enable SMIs. */
|
||||
outw(0x0, ACPI_IO_BASE + 0x2a);
|
||||
|
||||
/* All SMI off, both IDE buses ON, PSON rising edge. */
|
||||
outw(0x0, ACPI_IO_BASE + 0x2c);
|
||||
|
||||
/* Primary activity SMI disable. */
|
||||
outl(0x0, ACPI_IO_BASE + 0x34);
|
||||
|
||||
/* GP timer reload on none. */
|
||||
outl(0x0, ACPI_IO_BASE + 0x38);
|
||||
|
||||
/* Disable extended IO traps. */
|
||||
outb(0x0, ACPI_IO_BASE + 0x42);
|
||||
|
||||
/* SCI is generated for RTC/pwrBtn/slpBtn. */
|
||||
outw(0x0001, ACPI_IO_BASE + 0x04);
|
||||
|
||||
/* Allow SLP# signal to assert LDTSTOP_L.
|
||||
* Will work for C3 and for FID/VID change.
|
||||
*/
|
||||
outb(0x1, ACPI_IO_BASE + 0x11);
|
||||
}
|
||||
|
||||
static void cx700_set_lpc_registers(struct device *dev)
|
||||
{
|
||||
unsigned char enables;
|
||||
|
||||
printk(BIOS_DEBUG, "VIA CX700 LPC bridge init\n");
|
||||
|
||||
// enable the internal I/O decode
|
||||
enables = pci_read_config8(dev, 0x6C);
|
||||
enables |= 0x80;
|
||||
pci_write_config8(dev, 0x6C, enables);
|
||||
|
||||
// Map 4MB of FLASH into the address space
|
||||
|
||||
// Set bit 6 of 0x40, because Award does it (IO recovery time)
|
||||
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
|
||||
// interrupts can be properly marked as level triggered.
|
||||
enables = pci_read_config8(dev, 0x40);
|
||||
enables |= 0x44;
|
||||
pci_write_config8(dev, 0x40, enables);
|
||||
|
||||
/* DMA Line buffer control */
|
||||
enables = pci_read_config8(dev, 0x42);
|
||||
enables |= 0xf0;
|
||||
pci_write_config8(dev, 0x42, enables);
|
||||
|
||||
/* I/O recovery time */
|
||||
pci_write_config8(dev, 0x4c, 0x44);
|
||||
|
||||
/* ROM memory cycles go to LPC. */
|
||||
pci_write_config8(dev, 0x59, 0x80);
|
||||
|
||||
/* Enable SM dynamic clock gating */
|
||||
pci_write_config8(dev, 0x5b, 0x01);
|
||||
|
||||
/* Set Read Pass Write Control Enable */
|
||||
pci_write_config8(dev, 0x48, 0x0c);
|
||||
|
||||
/* Set SM Misc Control: Enable Internal APIC . */
|
||||
enables = pci_read_config8(dev, 0x58);
|
||||
enables |= 1 << 6;
|
||||
pci_write_config8(dev, 0x58, enables);
|
||||
enables = pci_read_config8(dev, 0x4d);
|
||||
enables |= 1 << 3;
|
||||
pci_write_config8(dev, 0x4d, enables);
|
||||
|
||||
/* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */
|
||||
enables = pci_read_config8(dev, 0x4f);
|
||||
enables |= 0x08;
|
||||
pci_write_config8(dev, 0x4f, enables);
|
||||
|
||||
/* enable KBC configuration */
|
||||
pci_write_config8(dev, 0x51, 0x1f);
|
||||
|
||||
/* enable serial irq */
|
||||
pci_write_config8(dev, 0x52, 0x9);
|
||||
|
||||
/* dma */
|
||||
pci_write_config8(dev, 0x53, 0x00);
|
||||
|
||||
// Power management setup
|
||||
setup_pm(dev);
|
||||
|
||||
/* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */
|
||||
pci_write_config8(dev, 0x40, 0x54);
|
||||
|
||||
/* Enable HPET timer */
|
||||
pci_write_config32(dev, 0x68, (1 << 31) | (CONFIG_HPET_ADDRESS >> 8));
|
||||
|
||||
}
|
||||
|
||||
static void cx700_read_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
/* Make sure we call our childrens set/enable functions - these
|
||||
* are not called unless this device has a resource to set.
|
||||
*/
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
res = new_resource(dev, 1);
|
||||
res->base = 0x0UL;
|
||||
res->size = 0x400UL;
|
||||
res->limit = 0xffffUL;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = IO_APIC_ADDR;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
static void cx700_set_resources(struct device *dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
resource = find_resource(dev, 1);
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void cx700_enable_resources(struct device *dev)
|
||||
{
|
||||
/* Enable SuperIO decoding */
|
||||
pci_dev_enable_resources(dev);
|
||||
}
|
||||
|
||||
static void cx700_lpc_init(struct device *dev)
|
||||
{
|
||||
cx700_set_lpc_registers(dev);
|
||||
|
||||
#if IS_ENABLED(CONFIG_IOAPIC)
|
||||
#define IO_APIC_ID 2
|
||||
setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID);
|
||||
#endif
|
||||
|
||||
/* Initialize interrupts */
|
||||
pci_routing_fixup(dev);
|
||||
/* make sure interupt controller is configured before keyboard init */
|
||||
setup_i8259();
|
||||
|
||||
/* Start the Real Time Clock */
|
||||
cmos_init(0);
|
||||
|
||||
/* Initialize isa dma */
|
||||
isa_dma_init();
|
||||
|
||||
/* Initialize keyboard controller */
|
||||
pc_keyboard_init(NO_AUX_DEVICE);
|
||||
}
|
||||
|
||||
static struct device_operations cx700_lpc_ops = {
|
||||
.read_resources = cx700_read_resources,
|
||||
.set_resources = cx700_set_resources,
|
||||
.enable_resources = cx700_enable_resources,
|
||||
.init = cx700_lpc_init,
|
||||
.scan_bus = scan_lpc_bus,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &cx700_lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = 0x8324,
|
||||
};
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cbmem.h>
|
||||
#include <arch/acpi.h>
|
||||
|
||||
static void pci_domain_set_resources(struct device *dev)
|
||||
{
|
||||
struct device *mc_dev;
|
||||
u32 pci_tolm;
|
||||
unsigned char reg;
|
||||
unsigned long tomk, tolmk;
|
||||
unsigned char rambits;
|
||||
int idx;
|
||||
|
||||
pci_tolm = find_pci_tolm(dev->link_list);
|
||||
mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
|
||||
|
||||
rambits = pci_read_config8(mc_dev, 0x88);
|
||||
rambits >>= 2;
|
||||
|
||||
/* Get memory size and frame buffer from northbridge's registers.
|
||||
*
|
||||
* If register contains an invalid value we set frame buffer size to a
|
||||
* default of 32M, but that probably won't happen.
|
||||
*/
|
||||
reg = pci_read_config8(mc_dev, 0xa1);
|
||||
reg &= 0x70;
|
||||
reg = reg >> 4;
|
||||
|
||||
/* TOP 1M SMM Memory */
|
||||
if (reg == 0x0 || reg == 0x6 || reg == 0x7)
|
||||
tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default
|
||||
else
|
||||
tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
|
||||
|
||||
/* Compute the top of Low memory */
|
||||
tolmk = pci_tolm >> 10;
|
||||
if (tolmk >= tomk) {
|
||||
/* The PCI hole does does not overlap the memory. */
|
||||
tolmk = tomk;
|
||||
tolmk -= 1024; // TOP 1M SM Memory
|
||||
}
|
||||
|
||||
set_late_cbmem_top(tolmk * 1024);
|
||||
|
||||
/* Report the memory regions */
|
||||
idx = 10;
|
||||
|
||||
/* TODO: Hole needed? Should this go elsewhere? */
|
||||
ram_resource(dev, idx++, 0, 640); /* first 640k */
|
||||
ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */
|
||||
assign_resources(dev->link_list);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
struct device *dev;
|
||||
u64 mmcfg;
|
||||
|
||||
dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0
|
||||
if (!dev)
|
||||
return current;
|
||||
|
||||
// MMCFG not supported or not enabled.
|
||||
if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0)
|
||||
return current;
|
||||
|
||||
mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28;
|
||||
if (!mmcfg)
|
||||
return current;
|
||||
|
||||
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.write_acpi_tables = acpi_write_hpet,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(struct device *dev)
|
||||
{
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = DEVICE_NOOP,
|
||||
.set_resources = DEVICE_NOOP,
|
||||
.enable_resources = DEVICE_NOOP,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
/* Our wonderful device model */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_via_cx700_ops = {
|
||||
CHIP_NAME("VIA CX700 Northbridge")
|
||||
.enable_dev = enable_dev
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,24 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 2
|
||||
|
||||
struct mem_controller {
|
||||
u16 channel0[DIMM_SOCKETS];
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __VIA_CX700_REGISTERS_H__
|
||||
#define __VIA_CX700_REGISTERS_H__
|
||||
|
||||
/* CX700 has 48 bytes of scratch registers in D0F4 starting at Reg. 0xd0 */
|
||||
#define SCRATCH_REG_BASE 0xd0
|
||||
#define SCRATCH_RANK_0 0xd0
|
||||
#define SCRATCH_RANK_1 0xd1
|
||||
#define SCRATCH_RANK_2 0xd2
|
||||
#define SCRATCH_RANK_3 0xd3
|
||||
#define SCRATCH_DIMM_NUM 0xd4
|
||||
#define SCRATCH_RANK_NUM 0xd5
|
||||
#define SCRATCH_RANK_MAP 0xd6
|
||||
#define SCRATCH_DRAM_FREQ 0xd7
|
||||
#define SCRATCH_DRAM_NB_ODT 0xd8
|
||||
#define SCRATCH_RANK0_SIZE_REG 0xe0 /* RxE0~RxE3 */
|
||||
#define SCRATCH_RANK0_MA_REG 0xe4 /* RxE4~RxE7 */
|
||||
#define SCRATCH_CHA_DQSI_LOW_REG 0xe8
|
||||
#define SCRATCH_CHA_DQSI_HIGH_REG 0xe9
|
||||
#define SCRATCH_ChA_DQSI_REG 0xea
|
||||
#define SCRATCH_DRAM_256M_BIT 0xee
|
||||
#define SCRATCH_FLAGS 0xef
|
||||
|
||||
#define DDRII_666 0x5
|
||||
#define DDRII_533 0x4
|
||||
#define DDRII_400 0x3
|
||||
#define DDRII_333 0x2
|
||||
#define DDRII_266 0x1
|
||||
#define DDRII_200 0x0
|
||||
|
||||
#endif
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <reset.h>
|
||||
|
||||
void do_hard_reset(void)
|
||||
{
|
||||
outb((1 << 2) | (1 << 1), 0xcf9);
|
||||
}
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
/* IDE specific bits */
|
||||
#define IDE_MODE_REG 0x09
|
||||
#define IDE0_NATIVE_MODE (1 << 0)
|
||||
#define IDE1_NATIVE_MODE (1 << 2)
|
||||
|
||||
/* These are default addresses */
|
||||
#define IDE0_DATA_ADDR 0x1f0
|
||||
#define IDE0_CONTROL_ADDR 0x3f4
|
||||
#define IDE1_DATA_ADDR 0x170
|
||||
#define IDE1_CONTROL_ADDR 0x370
|
||||
|
||||
#define BUS_MASTER_ADDR 0xfc00
|
||||
|
||||
#define CHANNEL_ENABLE_REG 0x40
|
||||
#define ENABLE_IDE0 (1 << 0)
|
||||
#define ENABLE_IDE1 (1 << 1)
|
||||
|
||||
/* TODO: better user configuration */
|
||||
#define DISABLE_SATA 0
|
||||
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
printk(BIOS_DEBUG, "Configuring VIA SATA & EIDE Controller\n");
|
||||
|
||||
/* Class IDE Disk, instead of RAID controller */
|
||||
reg8 = pci_read_config8(dev, 0x45);
|
||||
reg8 &= 0x7f; /* Sub Class Write Protect off */
|
||||
pci_write_config8(dev, 0x45, reg8);
|
||||
pci_write_config8(dev, 0x0a, 0x01);
|
||||
reg8 |= 0x80; /* Sub Class Write Protect on */
|
||||
pci_write_config8(dev, 0x45, reg8);
|
||||
|
||||
#if defined(DISABLE_SATA) && (DISABLE_SATA == 1)
|
||||
printk(BIOS_INFO, "Disabling SATA (Primary Channel)\n");
|
||||
/* Disable SATA channels */
|
||||
pci_write_config8(dev, 0x40, 0x00);
|
||||
#else
|
||||
pci_write_config8(dev, 0x40, 0x43);
|
||||
#endif
|
||||
|
||||
reg8 = pci_read_config8(dev, 0x6a);
|
||||
reg8 |= 0x8; /* Mode Select set to Manual Mode */
|
||||
reg8 &= ~7;
|
||||
reg8 |= 0x2; /* Manual setting to 50 ohm */
|
||||
|
||||
pci_write_config8(dev, 0x6a, reg8);
|
||||
|
||||
reg8 = pci_read_config8(dev, 0x6b);
|
||||
reg8 &= ~7;
|
||||
reg8 |= 0x01; /* Autocomp of Termination */
|
||||
pci_write_config8(dev, 0x6b, reg8);
|
||||
|
||||
/* Enable EIDE (secondary channel) even if SATA disabled */
|
||||
reg8 = pci_read_config8(dev, 0xc0);
|
||||
reg8 |= 0x1;
|
||||
pci_write_config8(dev, 0xc0, reg8);
|
||||
|
||||
// Enable bus mastering, memory space acces, io space access
|
||||
pci_write_config16(dev, 0x04, 0x0007);
|
||||
|
||||
/* Set SATA base ports. */
|
||||
pci_write_config32(dev, 0x10, 0x01f1);
|
||||
pci_write_config32(dev, 0x14, 0x03f5);
|
||||
/* Set EIDE base ports. */
|
||||
pci_write_config32(dev, 0x18, 0x0171);
|
||||
pci_write_config32(dev, 0x1c, 0x0375);
|
||||
|
||||
/* SATA/EIDE Bus Master mode base address */
|
||||
pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
|
||||
|
||||
/* Enable read/write prefetch buffers */
|
||||
reg8 = pci_read_config8(dev, 0xc1);
|
||||
reg8 |= 0x30;
|
||||
pci_write_config8(dev, 0xc1, reg8);
|
||||
|
||||
/* Set FIFO thresholds like */
|
||||
pci_write_config8(dev, 0xc3, 0x1); /* FIFO flushed when 1/2 full */
|
||||
|
||||
/* EIDE Sector Size */
|
||||
pci_write_config16(dev, 0xe8, 0x200);
|
||||
|
||||
/* Some Miscellaneous Control */
|
||||
pci_write_config8(dev, 0x44, 0x7);
|
||||
pci_write_config8(dev, 0x45, 0xaf);
|
||||
pci_write_config8(dev, 0x46, 0x8);
|
||||
|
||||
/* EIDE Configuration */
|
||||
reg8 = pci_read_config8(dev, 0xc4);
|
||||
reg8 |= 0x10;
|
||||
pci_write_config8(dev, 0xc4, reg8);
|
||||
|
||||
pci_write_config8(dev, 0xc5, 0xc);
|
||||
|
||||
/* Interrupt Line */
|
||||
reg8 = pci_read_config8(dev, 0x45);
|
||||
reg8 &= ~(1 << 4); /* Interrupt Line Write Protect off */
|
||||
pci_write_config8(dev, 0x45, reg8);
|
||||
|
||||
pci_write_config8(dev, 0x3c, 0x0e); /* Interrupt */
|
||||
|
||||
/* Set the drive timing control */
|
||||
pci_write_config16(dev, 0x48, 0x5d5d);
|
||||
|
||||
/* Enable only compatibility mode. */
|
||||
reg8 = pci_read_config8(dev, 0x42);
|
||||
reg8 &= ~0xa0;
|
||||
pci_write_config8(dev, 0x42, reg8);
|
||||
reg8 = pci_read_config8(dev, 0x42);
|
||||
printk(BIOS_DEBUG, "Reg 0x42 read back as 0x%x\n", reg8);
|
||||
|
||||
/* Support Staggered Spin-Up */
|
||||
reg8 = pci_read_config8(dev, 0xb9);
|
||||
if ((reg8 & 0x8) == 0) {
|
||||
printk(BIOS_DEBUG, "start OOB sequence on both drives\n");
|
||||
reg8 |= 0x30;
|
||||
pci_write_config8(dev, 0xb9, reg8);
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations sata_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = sata_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
/* When the SATA controller is in IDE mode, the Device ID is 0x5324 */
|
||||
static const struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = 0x5324,
|
||||
};
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
u8 reg8;
|
||||
|
||||
/* USB Specification says the device must be Bus Master */
|
||||
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
|
||||
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
|
||||
|
||||
reg8 = pci_read_config8(dev, 0xca);
|
||||
reg8 |= (1 << 0);
|
||||
pci_write_config8(dev, 0xca, reg8);
|
||||
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = usb_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver via_usb_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = 0x3038,
|
||||
};
|
||||
|
|
@ -1,209 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <arch/interrupt.h>
|
||||
#include "registers.h"
|
||||
#include <x86emu/regs.h>
|
||||
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
|
||||
#include <device/oprom/realmode/x86.h>
|
||||
#endif
|
||||
|
||||
/* PCI Domain 1 Device 0 Function 0 */
|
||||
|
||||
#define SR_INDEX 0x3c4
|
||||
#define SR_DATA 0x3c5
|
||||
#define CRTM_INDEX 0x3b4
|
||||
#define CRTM_DATA 0x3b5
|
||||
#define CRTC_INDEX 0x3d4
|
||||
#define CRTC_DATA 0x3d5
|
||||
|
||||
static int via_cx700_int15_handler(void)
|
||||
{
|
||||
int res = 0;
|
||||
u8 mem_speed;
|
||||
|
||||
#define MEMORY_SPEED_66MHZ (0 << 4)
|
||||
#define MEMORY_SPEED_100MHZ (1 << 4)
|
||||
#define MEMORY_SPEED_133MHZ (1 << 4)
|
||||
#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200
|
||||
#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266
|
||||
#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333
|
||||
#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400
|
||||
#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533
|
||||
#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667
|
||||
|
||||
const u8 memory_mapping[6] = {
|
||||
MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ,
|
||||
MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ,
|
||||
MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ
|
||||
};
|
||||
|
||||
printk(BIOS_DEBUG, "via_cx700_int15_handler\n");
|
||||
|
||||
switch(X86_EAX & 0xffff) {
|
||||
case 0x5f00: /* VGA POST Initialization Signal */
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
case 0x5f01: /* Software Panel Type Configuration */
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
// panel type = 2 = 1024 * 768
|
||||
X86_ECX = (X86_ECX & 0xffffff00 ) | 2;
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
case 0x5f27: /* Boot Device Selection */
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
|
||||
X86_EBX = 0x00000000; // 0 -> default
|
||||
X86_ECX = 0x00000000; // 0 -> default
|
||||
// TV Layout - default
|
||||
X86_EDX = (X86_EDX & 0xffffff00) | 0;
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
case 0x5f0b: /* Get Expansion Setting */
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
|
||||
X86_ECX = X86_ECX & 0xffffff00; // non-expansion
|
||||
// regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
case 0x5f0f: /* VGA Post Completion */
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
case 0x5f18:
|
||||
X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
|
||||
#define UMA_SIZE_8MB (3 << 0)
|
||||
#define UMA_SIZE_16MB (4 << 0)
|
||||
#define UMA_SIZE_32MB (5 << 0)
|
||||
|
||||
X86_EBX = (X86_EBX & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB;
|
||||
|
||||
mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ);
|
||||
if (mem_speed > 5)
|
||||
mem_speed = 5;
|
||||
|
||||
X86_EBX |= memory_mapping[mem_speed];
|
||||
|
||||
res = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
|
||||
X86_EAX & 0xffff);
|
||||
break;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
#ifdef UNUSED_CODE
|
||||
static void write_protect_vgabios(void)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
printk(BIOS_DEBUG, "write_protect_vgabios\n");
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
|
||||
if (dev)
|
||||
pci_write_config8(dev, 0x80, 0xff);
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0);
|
||||
if (dev)
|
||||
pci_write_config8(dev, 0x61, 0xff);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void vga_enable_console(void)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
|
||||
/* Call VGA BIOS int10 function 0x4f14 to enable main console
|
||||
* Epia-M does not always autosense the main console so forcing
|
||||
* it on is good.
|
||||
*/
|
||||
|
||||
/* int#, EAX, EBX, ECX, EDX, ESI, EDI */
|
||||
realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void vga_init(struct device *dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
|
||||
|
||||
//*
|
||||
pci_write_config8(dev, 0x04, 0x07);
|
||||
pci_write_config8(dev, 0x3e, 0x02);
|
||||
pci_write_config8(dev, 0x0d, 0x40);
|
||||
pci_write_config32(dev, 0x10, 0xa0000008);
|
||||
pci_write_config32(dev, 0x14, 0xdd000000);
|
||||
pci_write_config8(dev, 0x3c, 0x0b);
|
||||
//*/
|
||||
|
||||
printk(BIOS_DEBUG, "Initializing VGA...\n");
|
||||
|
||||
pci_dev_init(dev);
|
||||
|
||||
if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return;
|
||||
|
||||
printk(BIOS_DEBUG, "Enable VGA console\n");
|
||||
vga_enable_console();
|
||||
|
||||
/* It's not clear if these need to be programmed before or after
|
||||
* the VGA bios runs. Try both, clean up later */
|
||||
/* Set memory rate to 200MHz */
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
reg8 = inb(CRTM_DATA);
|
||||
reg8 &= 0x0f;
|
||||
reg8 |= (0x3 << 4);
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
outb(reg8, CRTM_DATA);
|
||||
|
||||
/* Set framebuffer size to 32mb */
|
||||
reg8 = (32 / 4);
|
||||
outb(0x39, SR_INDEX);
|
||||
outb(reg8, SR_DATA);
|
||||
}
|
||||
|
||||
static struct device_operations vga_operations = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = vga_init,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver vga_driver __pci_driver = {
|
||||
.ops = &vga_operations,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = 0x3157,
|
||||
};
|
||||
Loading…
Reference in New Issue