diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 2380cdf61e..8f1d75ce64 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -24,6 +24,7 @@
  • Enable Serial Output"
  • Get the Previous Sleep State
  • Add the MemoryInit Support
  • +
  • Disable the Shadow ROM
  • Ramstage @@ -389,6 +390,17 @@ Use the following steps to debug the call to TempRamInit: +

    Disable Shadow ROM

    +

    + A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. + This shadow needs to be disabled to allow RAM to properly respond to + this address range. +

    +
      +
    1. Edit romstage/romstage.c and add the soc_after_ram_init routine
    2. +
    + +

    Ramstage

    @@ -717,6 +729,6 @@ Use the following steps to debug the call to TempRamInit:
    -

    Modified: 28 February 2016

    +

    Modified: 4 March 2016

    \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 7b82321266..a36acaa56a 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -94,6 +94,9 @@
  • +
  • Disable the + Shadow ROM +
  • Implement the .init routine for the chip operations @@ -198,6 +201,13 @@ for the PCI devices on the bus. + + ROM Shadow
    0x000E0000 - 0x000FFFFF + + Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/soc_after_ram_init routine + + Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written + @@ -346,6 +356,6 @@
    -

    Modified: 24 February 2016

    +

    Modified: 4 March 2016

    \ No newline at end of file