mb/clevo/l140cu: Use proper indents
Use proper indents in the devicetree and align `end` keywords. Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Michael Niewöhner
parent
aed8169ebb
commit
e9da62a05f
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@ -64,16 +64,16 @@ chip soc/intel/cannonlake
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device domain 0 on
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subsystemid 0x1558 0x1401 inherit
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on # SA Thermal device
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register "Device4Enable" = "1"
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end
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on # USB xHCI
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
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@ -85,15 +85,15 @@ chip soc/intel/cannonlake
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.3 on
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.3 on # CNVi wifi
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end # CNVi wifi
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device pci 14.5 off end # SDCard
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device pci 15.0 on # I2C #0
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end
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device pci 14.5 off end # SDCard
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device pci 15.0 on # I2C #0
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN040D""
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register "generic.desc" = ""ELAN Touchpad""
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@ -103,16 +103,16 @@ chip soc/intel/cannonlake
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device i2c 15 on end
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end
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end
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on # SATA
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register "SataMode" = "Sata_AHCI"
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register "SataSalpSupport" = "1"
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# Port 2 (J_SSD2)
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@ -122,24 +122,24 @@ chip soc/intel/cannonlake
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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end
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 on # PCI Express Port 6
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 off end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 off end # PCI Express Port 5
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device pci 1c.5 on # PCI Express Port 6
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device pci 00.0 on end # x1 Card reader
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[3]" = "5"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 on # PCI Express Port 8
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 on # PCI Express Port 8
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chip drivers/wifi/generic
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device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
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end
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@ -150,7 +150,7 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[7]" = "1"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
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end
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device pci 1d.0 on # PCI Express Port 9
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device pci 1d.0 on # PCI Express Port 9
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device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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@ -159,10 +159,10 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[8]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
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end
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on # PCI Express Port 13
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 on # PCI Express Port 13
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device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
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register "PcieRpEnable[12]" = "1"
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register "PcieRpLtrEnable[12]" = "1"
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@ -171,14 +171,14 @@ chip soc/intel/cannonlake
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register "PcieRpSlotImplemented[12]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
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end
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on # LPC Interface
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x84: Decode 0x80 - 0x8F (Port 80)
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register "gen1_dec" = "0x000c0081"
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@ -192,13 +192,13 @@ chip soc/intel/cannonlake
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 hidden end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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device pci 1f.1 hidden end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 on # Intel HDA
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register "PchHdaAudioLinkHda" = "1"
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end
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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