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soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset 

Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI

This CL also enables HECI 1 in devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Lean Sheng Tan 2021-05-26 08:11:51 -07:00 committed by Werner Zeh
parent 542a2d908d
commit e9ee4390a5
2 changed files with 63 additions and 13 deletions
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14
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
View File

@ -12,11 +12,21 @@ chip soc/intel/elkhartlake
register "pmc_gpe0_dw1" = "GPP_F"
register "pmc_gpe0_dw2" = "GPP_E"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "SmbusEnable" = "1"
register "Heci2Enable" = "1"
# Display related UPDs
# Enable HPD for DDI ports C
register "DdiPortCHpd" = "1"
# Enable DDC for DDI ports C
register "DdiPortCDdc" = "1"
# Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1"
@ -104,6 +114,10 @@ chip soc/intel/elkhartlake
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
}"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device

62
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -15,18 +15,6 @@
#include <soc/soc_chip.h>
#include <string.h>
/*
* ME End of Post configuration
* 0 - Disable EOP.
* 1 - Send in PEI (Applicable for FSP in API mode)
* 2 - Send in DXE (Not applicable for FSP in API mode)
*/
enum {
EOP_DISABLE,
EOP_PEI,
EOP_DXE,
} EndOfPost;
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
PCH_DEVFN_I2C1,
@ -111,12 +99,60 @@ static void parse_devicetree(FSP_S_CONFIG *params)
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
struct device *dev;
FSP_S_CONFIG *params = &supd->FspsConfig;
struct soc_intel_elkhartlake_config *config = config_of_soc();
/* Parse device tree and fill in FSP UPDs */
parse_devicetree(params);
/* TODO: Update with UPD override as FSP matures */
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Check if IGD is present and fill Graphics init param accordingly */
dev = pcidev_path_on_root(SA_DEVFN_IGD);
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Display config */
params->DdiPortAHpd = config->DdiPortAHpd;
params->DdiPortADdc = config->DdiPortADdc;
params->DdiPortCHpd = config->DdiPortCHpd;
params->DdiPortCDdc = config->DdiPortCDdc;
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->PchLockDownGlobalSmi = 0;
params->PchLockDownBiosLock = 0;
params->PchLockDownBiosInterface = 0;
params->PchWriteProtectionEnable[0] = 0;
params->PchUnlockGpioPads = 1;
params->RtcMemoryLock = 0;
} else {
params->PchLockDownGlobalSmi = 1;
params->PchLockDownBiosLock = 1;
params->PchLockDownBiosInterface = 1;
params->PchWriteProtectionEnable[0] = 1;
params->PchUnlockGpioPads = 0;
params->RtcMemoryLock = 1;
}
/* Disable PAVP */
params->PavpEnable = 0;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = 1;
/* PCH Master Gating Control */
params->PchPostMasterClockGating = 1;
params->PchPostMasterPowerGating = 1;
/* HECI */
params->Heci3Enabled = config->Heci3Enable;
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);