Complete code for errata 343. Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010 says to set the register to 1 before CAR and to 0 after. We were setting it to 0 after CAR, but not to 1 before. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -88,6 +88,10 @@ static const struct {
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{ CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
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0x00000000, 1 << (33-32),
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0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
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{ BU_CFG2, AMD_DRBH_Cx , AMD_PTYPE_ALL,
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0x00000000, 1 << (35-32),
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0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram() ) */
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};
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