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soc/amd/common/block/include/amdblocks: Fix typos 

Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38980
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-02-18 19:00:32 +01:00 committed by Patrick Georgi
parent 22f8ee0f0e
commit e9f86c1016
2 changed files with 2 additions and 2 deletions
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2
src/soc/amd/common/block/include/amdblocks/gpio_banks.h
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@ -303,7 +303,7 @@ uintptr_t gpio_get_address(gpio_t gpio_num);
void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size);
/* Return the interrupt status and clear if set. */
int gpio_interrupt_status(gpio_t gpio);
/* Implemented by soc, provides table of avaialable GPIO mapping to Gevents */
/* Implemented by soc, provides table of available GPIO mapping to Gevents */
void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items);
/* May be implemented by soc to handle special cases */
void soc_gpio_hook(uint8_t gpio, uint8_t mux);

2
src/soc/amd/common/block/include/amdblocks/lpc.h
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@ -103,7 +103,7 @@
#define LPC_MEM_PORT0 0x60
/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers.
For ease of access, each sub-register is declared separetely. */
For ease of access, each sub-register is declared separately. */
#define LPC_WIDEIO_GENERIC_PORT 0x64
#define LPC_WIDEIO1_GENERIC_PORT 0x66
#define ROM_ADDRESS_RANGE1_START 0x68