arch/x86/ioapic: Split some ioapic utility functions
Change-Id: I70dfec900e8ce6630e61bc3fcbcfd88c097a5600 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <device/mmio.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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@ -21,7 +22,7 @@ static int ioapic_interrupt_count(void *ioapic_base)
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{
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/* Read the available number of interrupts. */
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int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
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if (ioapic_interrupts == 0xff)
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if (!ioapic_interrupts || ioapic_interrupts == 0xff)
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ioapic_interrupts = 23;
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ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
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entry, which is the number of interrupts
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@ -31,23 +32,21 @@ static int ioapic_interrupt_count(void *ioapic_base)
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return ioapic_interrupts;
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}
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void clear_ioapic(void *ioapic_base)
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static void clear_vectors(void *ioapic_base, u8 first, u8 last)
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{
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u32 low, high;
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u32 i, ioapic_interrupts;
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u8 i;
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printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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low = INT_DISABLED;
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high = NONE;
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for (i = 0; i < ioapic_interrupts; i++) {
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for (i = first; i <= last; i++) {
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io_apic_write(ioapic_base, i * 2 + 0x10, low);
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io_apic_write(ioapic_base, i * 2 + 0x11, high);
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n",
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i, high, low);
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}
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@ -57,15 +56,42 @@ void clear_ioapic(void *ioapic_base)
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}
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}
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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void clear_ioapic(void *ioapic_base)
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{
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clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
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}
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static void route_i8259_irq0(void *ioapic_base)
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{
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u32 bsp_lapicid = lapicid();
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u32 low, high;
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ASSERT(bsp_lapicid < 255);
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printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
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bsp_lapicid);
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/* Enable Virtual Wire Mode. Should this be LOGICAL_DEST instead? */
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low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
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high = bsp_lapicid << (56 - 32);
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io_apic_write(ioapic_base, 0x10, low);
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io_apic_write(ioapic_base, 0x11, high);
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low);
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}
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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{
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int i;
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printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n",
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ioapic_base);
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printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
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bsp_lapicid);
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if (ioapic_id) {
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printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
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@ -84,11 +110,7 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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static void load_vectors(void *ioapic_base)
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{
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u32 bsp_lapicid = lapicid();
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u32 low, high;
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u32 i, ioapic_interrupts;
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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int first = 1, last;
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if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) {
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/*
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@ -104,29 +126,10 @@ static void load_vectors(void *ioapic_base)
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io_apic_write(ioapic_base, 0x03, 0);
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}
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/* Enable Virtual Wire Mode. */
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low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
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high = bsp_lapicid << (56 - 32);
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route_i8259_irq0(ioapic_base);
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io_apic_write(ioapic_base, 0x10, low);
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io_apic_write(ioapic_base, 0x11, high);
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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0, high, low);
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low = INT_DISABLED;
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high = NONE;
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for (i = 1; i < ioapic_interrupts; i++) {
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io_apic_write(ioapic_base, i * 2 + 0x10, low);
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io_apic_write(ioapic_base, i * 2 + 0x11, high);
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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i, high, low);
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}
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last = ioapic_interrupt_count(ioapic_base) - 1;
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clear_vectors(ioapic_base, first, last);
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}
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void setup_ioapic(void *ioapic_base, u8 ioapic_id)
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