From ea3e6b06cc82a64d16616399362d373bfcef8a60 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 Jan 2021 16:09:43 -0800 Subject: [PATCH] soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous In case of CPU PCIe RPs, the RP numbers might not be contiguous for all the functions in a slot. Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as per the FSP expectations. Hence, this change updates the defintion of `struct pcie_rp_group` to include a `start` member which indicates the starting PCI function number within the group. All common functions for PCIe RP are accordingly updated to take the `start` member into account. Thus, in the above example, ADL can provide a cpu_rp_table as follows: { { .slot = PCIE_SLOT_6, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_1, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_6, .start = 2, .count = 1 }, } Since start defaults to 0 when uninitialized, current PCH RP group tables don't need to be updated. Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370 Reviewed-by: Nico Huber Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- .../block/include/intelblocks/pcie_rp.h | 22 +++++++++++++++---- .../intel/common/block/pcie/pcie_helpers.c | 9 ++++---- src/soc/intel/common/block/pcie/pcie_rp.c | 5 +++-- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 264c43f585..578a600e5b 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -10,15 +10,27 @@ * functions. * * `slot` is the PCI device/slot number of such a group. - * `count` is the number of functions within the group. It is assumed that - * the first group includes the RPs 1 to the first group's `count` and that - * adjacent groups follow without gaps in the numbering. + * `start` is the initial PCI function number within the group. This is useful in case the + * root port numbers are not contiguous within the slot. + * `count` is the number of functions within the group starting with the `start` function + * number. */ struct pcie_rp_group { unsigned int slot; + unsigned int start; unsigned int count; }; +static inline unsigned int rp_start_fn(const struct pcie_rp_group *group) +{ + return group->start; +} + +static inline unsigned int rp_end_fn(const struct pcie_rp_group *group) +{ + return group->start + group->count - 1; +} + /* * Update PCI paths of the root ports in the devicetree. * @@ -32,7 +44,9 @@ struct pcie_rp_group { * Call this once, after root ports have been reordered, but before PCI * enumeration. * - * `groups` points to a list of groups terminated by an entry with `count == 0`. + * `groups` points to a list of groups terminated by an entry with `count == 0`. It is assumed + * that the first group includes the RPs 1 to the first group's `count` and that adjacent groups + * follow without gaps in the numbering. */ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); diff --git a/src/soc/intel/common/block/pcie/pcie_helpers.c b/src/soc/intel/common/block/pcie/pcie_helpers.c index 31451d07f6..e8ed3be56d 100644 --- a/src/soc/intel/common/block/pcie/pcie_helpers.c +++ b/src/soc/intel/common/block/pcie/pcie_helpers.c @@ -5,14 +5,15 @@ #include #include -static uint32_t pcie_slot_enable_mask(unsigned int slot, unsigned int count) +static uint32_t pcie_slot_enable_mask(const struct pcie_rp_group *group) { uint32_t mask = 0; + unsigned int fn; unsigned int i; const struct device *dev; - for (i = 0; i < count; i++) { - dev = pcidev_on_root(slot, i); + for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { + dev = pcidev_on_root(group->slot, fn); if (is_dev_enabled(dev)) mask |= BIT(i); } @@ -32,7 +33,7 @@ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups) __func__); break; } - mask |= pcie_slot_enable_mask(group->slot, group->count) << offset; + mask |= pcie_slot_enable_mask(group) << offset; offset += group->count; } diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 85b218a4ab..1c69f2c355 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -54,7 +54,7 @@ static void pcie_rp_scan_groups(int mapping[], const struct pcie_rp_group *const const struct pcie_rp_group *group; for (group = groups; group->count; ++group) { unsigned int fn; - for (fn = 0; fn < group->count; ++fn) { + for (fn = rp_start_fn(group); fn <= rp_end_fn(group); ++fn) { const pci_devfn_t dev = PCI_DEV(0, group->slot, fn); const uint16_t did = pci_s_read_config16(dev, PCI_DEVICE_ID); if (did == 0xffff) { @@ -96,7 +96,8 @@ static bool pcie_rp_update_dev( const struct pcie_rp_group *group; for (group = groups; group->count; ++group) { if (PCI_SLOT(dev->path.pci.devfn) == group->slot && - PCI_FUNC(dev->path.pci.devfn) < group->count) + PCI_FUNC(dev->path.pci.devfn) >= rp_start_fn(group) && + PCI_FUNC(dev->path.pci.devfn) <= rp_end_fn(group)) break; offset += group->count; }