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mb/google/poppy: enable AER for PCIe root port 0 

Enable PCIe Advanced Error Reporting for PCIe root port 0.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Rizwan Qureshi 2017-09-06 19:08:23 +05:30 committed by Furquan Shaikh
parent 6a051f2b49
commit ea4649f65f
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
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@ -152,6 +152,8 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1# # RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[0]" = "1"
# RP 1, Enable Advanced Error Reporting
register PcieRpAdvancedErrorReporting[0] = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port