mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5G
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -4,6 +4,7 @@
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <fw_config.h>
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/* Pad configuration in ramstage for Pujjo */
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static const struct pad_config override_gpio_table[] = {
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@ -29,6 +30,36 @@ static const struct pad_config override_gpio_table[] = {
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PAD_CFG_GPO(GPP_H23, 1, DEEP),
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};
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/* Pad configuration in ramstage for Pujjoteen5 */
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static const struct pad_config override_5g_gpio_table[] = {
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/* A8 : WWAN_RF_DISABLE_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A12 : WWAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI_LOCK(GPP_A12, NONE, LOCK_CONFIG),
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/* D3 : WCAM_RST_L ==> NC */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO_LOCK(GPP_D6, 1, LOCK_CONFIG),
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/* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */
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PAD_CFG_GPO(GPP_D15, 1, DEEP),
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/* D16 : EN_PP1800_PP1200_WCAM_X ==> NC */
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PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
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/* D17 : NC ==> SD_WAKE_N */
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PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
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/* F12 : WWAN_RST_L */
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PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
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/* H19 : SOC_I2C_SUB_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
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/* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */
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PAD_CFG_GPO(GPP_H21, 1, DEEP),
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/* H22 : WCAM_MCLK_R ==> NC */
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PAD_NC(GPP_H22, NONE),
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/* H23 : WWAN_SAR_DETECT_ODL */
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PAD_CFG_GPO(GPP_H23, 1, DEEP),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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@ -61,6 +92,41 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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};
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/* Early pad configuration in bootblock for Pujjoteen5 */
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static const struct pad_config early_5g_gpio_table[] = {
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/*
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* WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
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* requirement. WWAN_EN must be asserted before WWAN_RST_L is released
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* (with min delay 0 ms), so this works as long as the pin used for
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* WWAN_EN comes before the pin used for WWAN_RST_L.
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*/
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 0, DEEP),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
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/* F12 : WWAN_RST_L */
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PAD_CFG_GPO(GPP_F12, 0, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 0, DEEP),
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/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */
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PAD_CFG_GPO(GPP_H21, 0, DEEP),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 1, DEEP),
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@ -68,15 +134,25 @@ static const struct pad_config romstage_gpio_table[] = {
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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if (fw_config_probe(FW_CONFIG(WWAN_5G, WWAN_5G_PRESENT))) {
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*num = ARRAY_SIZE(override_5g_gpio_table);
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return override_5g_gpio_table;
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} else {
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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if (fw_config_probe(FW_CONFIG(WWAN_5G, WWAN_5G_PRESENT))) {
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*num = ARRAY_SIZE(early_5g_gpio_table);
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return early_5g_gpio_table;
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} else {
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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