qcs405: Add GPIO API
Introduce new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Nitheesh Sekar
Patrick Georgi
parent
0ef562feee
commit
ea4c7d0719
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@ -6,21 +6,25 @@ bootblock-y += bootblock.c
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bootblock-y += timer.c
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bootblock-y += spi.c
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bootblock-y += mmu.c
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bootblock-y += gpio.c
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################################################################################
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verstage-y += timer.c
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verstage-y += spi.c
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verstage-y += gpio.c
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################################################################################
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romstage-y += timer.c
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romstage-y += spi.c
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romstage-y += cbmem.c
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romstage-y += gpio.c
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################################################################################
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ramstage-y += soc.c
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ramstage-y += timer.c
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ramstage-y += spi.c
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ramstage-y += cbmem.c
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ramstage-y += gpio.c
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################################################################################
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@ -0,0 +1,76 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018-2019 Qualcomm Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/mmio.h>
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#include <types.h>
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#include <console/console.h>
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#include <delay.h>
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#include <timer.h>
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#include <timestamp.h>
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#include <gpio.h>
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void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
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uint32_t drive_str, uint32_t enable)
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{
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uint32_t reg_val;
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) |
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((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
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((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
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((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
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write32(®s->cfg, reg_val);
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}
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void gpio_set(gpio_t gpio, int value)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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write32(®s->in_out, (!!value) << GPIO_IO_OUT_SHFT);
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}
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int gpio_get(gpio_t gpio)
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{
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struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
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return ((read32(®s->in_out) >> GPIO_IO_IN_SHFT) &
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GPIO_IO_IN_BMSK);
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}
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void gpio_input_pulldown(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_input_pullup(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_input(gpio_t gpio)
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{
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE);
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}
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void gpio_output(gpio_t gpio, int value)
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{
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gpio_set(gpio, value);
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gpio_configure(gpio, GPIO_FUNC_GPIO,
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GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2018-2019 Qualcomm Technologies
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
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#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__
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#include <stdint.h>
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#define QSPI_BASE 0x88DF000
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#define TLMM_EAST_TILE_BASE 0x7B00000
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#define TLMM_NORTH_TILE_BASE 0x1300000
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#define TLMM_SOUTH_TILE_BASE 0x1000000
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#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -17,7 +17,299 @@
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#define _SOC_QUALCOMM_QCS405_GPIO_H_
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#include <types.h>
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#include <soc/addressmap.h>
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typedef u32 gpio_t;
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typedef struct {
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u32 addr;
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} gpio_t;
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#define TLMM_TILE_SIZE 0x00400000
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#define TLMM_GPIO_OFF_DELTA 0x00001000
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#define TLMM_GPIO_TILE_NUM 3
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#define TLMM_GPIO_IN_OUT_OFF 0x4
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#define TLMM_GPIO_ID_STATUS_OFF 0x10
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/* GPIO TLMM: Direction */
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#define GPIO_INPUT 0
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#define GPIO_OUTPUT 1
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/* GPIO TLMM: Pullup/Pulldown */
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#define GPIO_NO_PULL 0
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#define GPIO_PULL_DOWN 1
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#define GPIO_KEEPER 2
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#define GPIO_PULL_UP 3
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/* GPIO TLMM: Drive Strength */
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#define GPIO_2MA 0
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#define GPIO_4MA 1
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#define GPIO_6MA 2
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#define GPIO_8MA 3
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#define GPIO_10MA 4
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#define GPIO_12MA 5
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#define GPIO_14MA 6
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#define GPIO_16MA 7
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/* GPIO TLMM: Status */
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#define GPIO_DISABLE 0
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#define GPIO_ENABLE 1
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/* GPIO TLMM: Mask */
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#define GPIO_CFG_PULL_BMSK 0x3
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#define GPIO_CFG_FUNC_BMSK 0xF
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#define GPIO_CFG_DRV_BMSK 0x7
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#define GPIO_CFG_OE_BMSK 0x1
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/* GPIO TLMM: Shift */
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#define GPIO_CFG_PULL_SHFT 0
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#define GPIO_CFG_FUNC_SHFT 2
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#define GPIO_CFG_DRV_SHFT 6
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#define GPIO_CFG_OE_SHFT 9
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/* GPIO IO: Mask */
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#define GPIO_IO_IN_BMSK 0x1
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#define GPIO_IO_OUT_BMSK 0x1
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/* GPIO IO: Shift */
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#define GPIO_IO_IN_SHFT 0
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#define GPIO_IO_OUT_SHFT 1
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/* GPIO ID STATUS: Mask */
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#define GPIO_ID_STATUS_BMSK 0x1
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/* GPIO MAX Valid # */
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#define GPIO_NUM_MAX 149
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#define GPIO_FUNC_GPIO 0
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#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})
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#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
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GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \
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GPIO##index##_FUNC_##func1 = 1, \
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GPIO##index##_FUNC_##func2 = 2, \
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GPIO##index##_FUNC_##func3 = 3, \
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GPIO##index##_FUNC_##func4 = 4, \
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GPIO##index##_FUNC_##func5 = 5, \
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GPIO##index##_FUNC_##func6 = 6, \
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GPIO##index##_FUNC_##func7 = 7
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enum {
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PIN(0, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(1, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(2, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(3, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(4, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(5, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(6, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(7, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(8, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(9, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(10, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(11, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(12, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(17, NORTH, BLSP_UART_TX_A, BLSP_SPI_MOSI, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(18, NORTH, BLSP_UART_RX_A, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
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RES_6, RES_7),
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PIN(19, NORTH, BLSP_UART_CTS_N, AUD_CDC_INT2, RES_3, BLSP_SPI_CS_N,
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RES_5, RES_6, RES_7),
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PIN(20, NORTH, BLSP_UART_RFR_N, RES_2, RES_3, BLSP_SPI_CLK, RES_5,
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RES_6, RES_7),
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PIN(21, SOUTH, M_VOC_EXT_VFR_REF_IRQ_2, RES_2, RES_3, RES_4,
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RES_5, RES_6, RES_7),
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PIN(22, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI_A, ASDIV1, RES_4,
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RES_5, RES_6, RES_7),
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PIN(23, NORTH, BLSP_UART_RX, BLSP_SPI_MISO_A, ASDIV2, RES_4,
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RES_5, RES_6, RES_7),
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PIN(24, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N_A,
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RES_4, RES_5, RES_6, RES_7),
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PIN(25, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK_A,
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RES_4, RES_5, RES_6, RES_7),
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PIN(26, EAST, RES_1, BLSP_UART_TX, BLSP_SPI_MOSI, RES_4, RES_5,
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RES_6, RES_7),
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PIN(27, EAST, RES_1, BLSP_UART_RX, BLSP_SPI_MISO, RES_4, RES_5,
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RES_6, RES_7),
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PIN(28, EAST, RES_1, BLSP_UART_CTS_N, RES_3, BLSP_SPI_CS_N, RES_5,
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RES_6, RES_7),
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PIN(29, EAST, RES_1, BLSP_UART_RFR_N, RES_3, BLSP_SPI_CLK, RES_5,
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RES_6, RES_7),
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PIN(30, NORTH, RES_1, BLSP_UART_TX, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(31, NORTH, RES_1, BLSP_UART_RX, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(32, NORTH, RES_1, BLSP_UART_CTS_N, BLSP_I2C_SDA, RES_4, RES_5,
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RES_6, RES_7),
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PIN(33, NORTH, RES_1, BLSP_UART_RFR_N, BLSP_I2C_SCL, RES_4, RES_5,
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RES_6, RES_7),
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PIN(34, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(35, SOUTH, PCIE_CLK_REQ, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(36, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(37, NORTH, NFC_IRQ, BLSP_SPI_MOSI, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(38, NORTH, RES_1, BLSP_SPI_MISO, AUDIO_TS_IN, RES_4, RES_5,
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RES_6, RES_7),
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PIN(39, EAST, RES_1, RES_2, BLSP_UART_TX_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(40, EAST, RES_1, RES_2, BLSP_UART_RX_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(41, EAST, RES_1, BLSP_I2C_SDA_B, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(42, EAST, RES_1, BLSP_I2C_SCL_B, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(43, EAST, RES_1, PWM_LED11, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(44, EAST, RES_1, PWM_LED12, BLSP_SPI_CS1_N, RES_4, RES_5,
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RES_6, RES_7),
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PIN(45, EAST, RES_1, PWM_LED13, BLSP_SPI_CS2_N, RES_4, RES_5,
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RES_6, RES_7),
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PIN(46, EAST, RES_1, PWM_LED14, BLSP_SPI_CS3_N, RES_4, RES_5,
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RES_6, RES_7),
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PIN(47, EAST, RES_1, PWM_LED15, BLSP_SPI_MOSI_B, RES_4, RES_5,
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RES_6, RES_7),
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PIN(48, EAST, RES_1, PWM_LED16, BLSP_SPI_MISO_B, RES_4, RES_5,
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RES_6, RES_7),
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PIN(49, EAST, RES_1, PWM_LED17, BLSP_SPI_CS_N_B, RES_4, RES_5,
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RES_6, RES_7),
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PIN(50, EAST, RES_1, PWM_LED18, BLSP_SPI_CLK_B, RES_4, RES_5,
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RES_6, RES_7),
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PIN(51, EAST, RES_1, PWM_LED19, EXT_MCLK1_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(52, EAST, RES_1, PWM_LED20, RES_3, I2S_3_SCK_B, RES_5, RES_6,
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RES_7),
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PIN(53, EAST, RES_1, PWM_LED21, I2S_3_WS_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(54, EAST, RES_1, I2S_3_DATA0_B, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(55, EAST, RES_1, I2S_3_DATA1_B, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(56, EAST, RES_1, RES_2, I2S_3_DATA2_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(57, EAST, RES_1, RES_2, I2S_3_DATA3_B, RES_4, RES_5, RES_6,
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RES_7),
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PIN(58, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(59, EAST, RGB_DATA_B, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(60, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(61, NORTH, RGMII_INT, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(62, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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PIN(63, NORTH, RGMII_CK_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(64, NORTH, RGMII_TX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(65, NORTH, RGMII_TX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(66, NORTH, RGMII_TX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(67, NORTH, RGMII_TX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(68, NORTH, RGMII_CTL_TX, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(69, NORTH, RGMII_CK_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(70, NORTH, RGMII_RX_3, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(71, NORTH, RGMII_RX_2, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(72, NORTH, RGMII_RX_1, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
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PIN(73, NORTH, RGMII_RX_0, RES_2, RES_3, RES_4, RES_5, RES_6,
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RES_7),
|
||||
PIN(74, NORTH, RGMII_CTL_RX, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(75, NORTH, RGMII_MDIO, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(76, NORTH, RGMII_MDC, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(77, NORTH, IR_IN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(78, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(79, EAST, RGB_DATA_G, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(80, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(81, EAST, RGB_DATA_R, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(82, NORTH, BLSP_UART_TX, BLSP_SPI_MOSI, SD_WRITE_PROTECT,
|
||||
RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(83, NORTH, BLSP_UART_RX, BLSP_SPI_MISO, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(84, NORTH, BLSP_UART_CTS_N, BLSP_I2C_SDA, BLSP_SPI_CS_N,
|
||||
RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(85, NORTH, BLSP_UART_RFR_N, BLSP_I2C_SCL, BLSP_SPI_CLK, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(86, EAST, RES_1, MCLK_IN1, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(87, EAST, I2S_1_SCK, DSD_CLK_A, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(88, EAST, I2S_1_WS, I2S_1_DATA0_DSD0, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(89, EAST, I2S_1_DATA0, I2S_1_DATA1_DSD1, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(90, EAST, I2S_1_DATA1, I2S_1_DATA2_DSD2, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(91, EAST, I2S_1_DATA2, I2S_1_DATA3_DSD3, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(92, EAST, I2S_1_DATA3, I2S_1_DATA4_DSD4, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(93, EAST, I2S_1_DATA4, PWM_LED22, I2S_1_DATA5_DSD5, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(94, EAST, I2S_1_DATA5, PWM_LED23, I2S_1_DATA6_MIR, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(95, EAST, RES_1, PWM_LED1, I2S_1_DATA7_MIR, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(96, EAST, RES_1, PWM_LED2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(97, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(98, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(99, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(100, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(101, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(102, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(103, EAST, RES_1, MCLK_IN2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
PIN(104, EAST, I2S_3_SCK_A, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(105, EAST, I2S_3_WS_A, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(106, EAST, I2S_3_DATA0_A, RES_2, HDMI_HOT_PLUG_MIR, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(107, EAST, I2S_3_DATA1_A, RES_2, RES_3, RES_4, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(108, EAST, I2S_3_DATA2_A, RES_2, RES_3, PWM_LED3, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(109, EAST, I2S_3_DATA3_A, RES_2, PWM_LED4, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(110, EAST, RES_1, RES_2, DSD_CLK_B, PWM_LED5, RES_5, RES_6,
|
||||
RES_7),
|
||||
PIN(111, EAST, RES_1, I2S_4_DATA0_DSD0, PWM_LED6, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(112, EAST, RES_1, I2S_4_DATA1_DSD1, PWM_LED7, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(113, EAST, RES_1, I2S_4_DATA2_DSD2, PWM_LED8, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(114, EAST, RES_1, I2S_4_DATA3_DSD3, PWM_LED24, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(115, EAST, RES_1, I2S_4_DATA4_DSD4, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(116, EAST, I2S_4_DATA5_DSD5, SPKR_DAC0, RES_3, RES_4, RES_5,
|
||||
RES_6, RES_7),
|
||||
PIN(117, NORTH, BLSP_I2C_SDA, BLSP_SPI_CS_N, PWM_LED9, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(118, NORTH, BLSP_I2C_SCL, BLSP_SPI_CLK, PWM_LED10, RES_4,
|
||||
RES_5, RES_6, RES_7),
|
||||
PIN(119, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
|
||||
};
|
||||
|
||||
struct tlmm_gpio {
|
||||
uint32_t cfg;
|
||||
uint32_t in_out;
|
||||
};
|
||||
|
||||
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
|
||||
uint32_t drive_str, uint32_t enable);
|
||||
|
||||
#endif // _SOC_QUALCOMM_QCS405_GPIO_H_
|
||||
|
|
|
|||
Loading…
Reference in New Issue