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Documentation/mainboard/facebook/monolith.md: Update to beta status 

Update to reflect the beta status of the code.

BUG=N/A
TEST=build

Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Wim Vervoorn 2020-01-28 16:43:45 +01:00 committed by Patrick Georgi
parent b52354b6be
commit ea4d1246e8
1 changed files with 27 additions and 10 deletions
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37
Documentation/mainboard/facebook/monolith.md
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@ -3,15 +3,28 @@
This page describes how to run coreboot on the Facebook Monolith. This page describes how to run coreboot on the Facebook Monolith.
Please note: the coreboot implementation for this boards is in its Please note: the coreboot implementation for this boards is in its
Alpha state and isn't fully tested yet. Beta state and isn't fully tested yet.
## Required blobs ## Required blobs
This board currently requires: Mainboard is based on the Intel Kaby Lake U SoC.
fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md)
3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd (intel FSP 2.0) to initialize this generation silicon. Please see this
[document](../../soc/intel/code_development_model/code_development_model.md).
Microcode 3rdparty/intel-microcode/intel-ucode FSP Information:
```eval_rst
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
| processors and chipsets | | |
| (formerly Kaby Lake) | | |
+-----------------------------+-------------------+-------------------+
```
Microcode: 3rdparty/intel-microcode/intel-ucode
## Flash components ## Flash components
@ -75,25 +88,29 @@ solution. Wires need to be connected to be able to flash using an external progr
## Untested ## Untested
- Hardware monitor - Hardware monitor
- SDIO
- Full Embedded Controller support - Full Embedded Controller support
- eMMC
- SATA - SATA
- xDCI
## Working ## Working
- USB - USB
- Gigabit Ethernet - Gigabit Ethernet (i219 and i210)
- Graphics (Using FSP GOP) - Graphics (Using FSP GOP)
- flashrom - flashrom
- PCIe - PCIe including hotplug on FPGA root port
- EC serial port - EC serial port
- EC CPU temperature
- SMBus - SMBus
- Initialization with FSP - Initialization with FSP
- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) - TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
- LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
- eMMC
All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
and LinuxBoot.
All of the above has been briefly tested by booting Linux from the TianoCore payload.
SeaBios has been checked to the extend that it runs to the boot selection and provides display SeaBios has been checked to the extend that it runs to the boot selection and provides display
output. output.