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arch/x86,cpu/x86: Disable the %gs and %fs segments 

The %fs and %gs segment are typically used to implement thread local
storage or cpu local storage. We don't currently use these in coreboot,
so there is no reason to map them. By setting the segment index to 0,
it disables the segment. If an instruction tries to read from one of
these segments an exception will be raised.

The end goal is to make cpu_info() use the %gs segment. This will remove
the stack alignment requirements and fix smm_do_relocation.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Raul E Rangel 2021-09-21 10:17:24 -06:00 committed by Felix Held
parent 326a2c4794
commit ea5c31138b
6 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/x86/c_start.S
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@ -39,8 +39,9 @@ _start:
movl %eax, %ds movl %eax, %ds
movl %eax, %es movl %eax, %es
movl %eax, %ss movl %eax, %ss
xor %eax, %eax /* zero out the gs and fs segment index */
movl %eax, %fs movl %eax, %fs
movl %eax, %gs movl %eax, %gs /* Will be used for cpu_info */
#if ENV_X86_64 #if ENV_X86_64
mov $RAM_CODE_SEG64, %ecx mov $RAM_CODE_SEG64, %ecx
call SetCodeSelector call SetCodeSelector

3
src/cpu/x86/entry32.S
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@ -37,8 +37,9 @@ bootblock_protected_mode_entry:
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs movw %ax, %fs
movw %ax, %gs movw %ax, %gs /* Will be used for cpu_info */
/* Restore the BIST value to %eax */ /* Restore the BIST value to %eax */
movl %ebp, %eax movl %ebp, %eax

3
src/cpu/x86/lapic/secondary.S
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@ -52,8 +52,9 @@ __ap_protected_start:
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs movw %ax, %fs
movw %ax, %gs movw %ax, %gs /* Will be used for cpu_info */
/* Load the Interrupt descriptor table */ /* Load the Interrupt descriptor table */
lidt idtarg lidt idtarg

3
src/cpu/x86/sipi_vector.S
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@ -77,8 +77,9 @@ _start:
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs movw %ax, %fs
movw %ax, %gs movw %ax, %gs /* Will be used for cpu_info */
/* Load the Interrupt descriptor table */ /* Load the Interrupt descriptor table */
mov idt_ptr, %ebx mov idt_ptr, %ebx

3
src/cpu/x86/smm/smm_stub.S
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@ -93,8 +93,9 @@ smm_trampoline32:
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs movw %ax, %fs
movw %ax, %gs movw %ax, %gs /* Will be used for cpu_info */
/* The CPU number is calculated by reading the initial APIC id. Since /* The CPU number is calculated by reading the initial APIC id. Since
* the OS can manipulate the APIC id use the non-changing cpuid result * the OS can manipulate the APIC id use the non-changing cpuid result

3
src/cpu/x86/smm/smmhandler.S
View File

@ -123,8 +123,9 @@ untampered_lapic:
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
xor %ax, %ax /* zero out the gs and fs segment index */
movw %ax, %fs movw %ax, %fs
movw %ax, %gs movw %ax, %gs /* Will be used for cpu_info */
/* FIXME: Incompatible with X2APIC_SUPPORT. */ /* FIXME: Incompatible with X2APIC_SUPPORT. */
/* Get this CPU's LAPIC ID */ /* Get this CPU's LAPIC ID */