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soc/intel/xeon_sp: Add PM definition for SPR-SP 

Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
This commit is contained in:
David Hendricks 2023-03-04 16:19:35 -08:00 committed by Felix Held
parent 35860ffabe
commit ea643a81a1
3 changed files with 27 additions and 7 deletions
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13
src/soc/intel/xeon_sp/ebg/include/soc/soc_pm.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_EBG_PM_H_
#define _SOC_EBG_PM_H_
#define GPE0_STS(x) (0x60 + ((x) * 4))
#define GPE0_EN(x) (0x70 + ((x) * 4))
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
#define ETR 0x1048
#define PRSTS 0x1810
#endif /* _SOC_EBG_PM_H_ */

8
src/soc/intel/xeon_sp/include/soc/pm.h
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@ -7,6 +7,7 @@
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/pmc.h> #include <soc/pmc.h>
#include <soc/soc_pm.h>
/* ACPI_BASE_ADDRESS / PMBASE */ /* ACPI_BASE_ADDRESS / PMBASE */
#define PM1_STS 0x00 #define PM1_STS 0x00
@ -66,8 +67,6 @@
#define PM2_CNT 0x50 #define PM2_CNT 0x50
#define GPE0_REG_MAX 4 #define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32 #define GPE0_REG_SIZE 32
#define GPE0_STS(x) (0x80 + ((x) * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
#define GPE_STS_RSVD GPE_STD #define GPE_STS_RSVD GPE_STD
#define GPIO_T2_STS (1 << 15) #define GPIO_T2_STS (1 << 15)
@ -76,7 +75,6 @@
#define PCI_EXP_STS (1 << 9) #define PCI_EXP_STS (1 << 9)
#define SMB_WAK_STS (1 << 7) #define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6) #define TCOSCI_STS (1 << 6)
#define GPE0_EN(x) (0x90 + ((x) * 4))
#define GPIO_T2_EN (1 << 15) #define GPIO_T2_EN (1 << 15)
#define ESPI_EN (1 << 14) #define ESPI_EN (1 << 14)
#define PME_B0_EN (1 << 13) #define PME_B0_EN (1 << 13)
@ -93,13 +91,9 @@
#define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10 #define PSS_LATENCY_BUSMASTER 10
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
#define ETR 0xac
#define CF9_LOCK (1 << 31) #define CF9_LOCK (1 << 31)
#define CF9_GLB_RST (1 << 20) #define CF9_GLB_RST (1 << 20)
#define PRSTS 0x10
struct chipset_power_state { struct chipset_power_state {
uint16_t pm1_sts; uint16_t pm1_sts;
uint16_t pm1_en; uint16_t pm1_en;

13
src/soc/intel/xeon_sp/lbg/include/soc/soc_pm.h Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _SOC_LBG_PM_H_
#define _SOC_LBG_PM_H_
#define GPE0_STS(x) (0x80 + ((x) * 4))
#define GPE0_EN(x) (0x90 + ((x) * 4))
/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
#define ETR 0xac
#define PRSTS 0x10
#endif /* _SOC_LBG_PM_H_ */