Add support for the Nokia IP530.
It's currently its able to run coreboot + seabios + sgabios.
The following hardware works;
P3
i440BX northbridge
82371 southbridge
IDE normal disks + CF
The following hardware doesn't work:
4x NIC 21143-PD
2x PCMCIA PCI1225PDV
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Bertens
Uwe Hermann
parent
961a7b0c08
commit
ea6772d306
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@ -68,6 +68,8 @@ config VENDOR_NEC
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bool "NEC"
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bool "NEC"
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config VENDOR_NEWISYS
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config VENDOR_NEWISYS
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bool "Newisys"
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bool "Newisys"
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config VENDOR_NOKIA
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bool "Nokia"
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config VENDOR_NVIDIA
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config VENDOR_NVIDIA
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bool "NVIDIA"
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bool "NVIDIA"
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config VENDOR_OLPC
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config VENDOR_OLPC
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@ -271,6 +273,11 @@ config MAINBOARD_VENDOR
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default "Newisys"
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default "Newisys"
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depends on VENDOR_NEWISYS
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depends on VENDOR_NEWISYS
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config MAINBOARD_VENDOR
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string
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default "Nokia"
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depends on VENDOR_NOKIA
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config MAINBOARD_VENDOR
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config MAINBOARD_VENDOR
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string
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string
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default "NVIDIA"
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default "NVIDIA"
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@ -398,6 +405,7 @@ source "src/mainboard/mitac/Kconfig"
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source "src/mainboard/msi/Kconfig"
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source "src/mainboard/msi/Kconfig"
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source "src/mainboard/nec/Kconfig"
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source "src/mainboard/nec/Kconfig"
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source "src/mainboard/newisys/Kconfig"
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source "src/mainboard/newisys/Kconfig"
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source "src/mainboard/nokia/Kconfig"
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source "src/mainboard/nvidia/Kconfig"
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source "src/mainboard/nvidia/Kconfig"
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source "src/mainboard/olpc/Kconfig"
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source "src/mainboard/olpc/Kconfig"
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source "src/mainboard/pcengines/Kconfig"
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source "src/mainboard/pcengines/Kconfig"
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@ -0,0 +1,28 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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choice
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prompt "Mainboard model"
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depends on VENDOR_NOKIA
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source "src/mainboard/nokia/ip530/Kconfig"
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endchoice
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@ -0,0 +1,52 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config BOARD_NOKIA_IP530
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bool "IP530"
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select ARCH_X86
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select CPU_INTEL_SOCKET_PGA370
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select NORTHBRIDGE_INTEL_I440BX
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select SOUTHBRIDGE_INTEL_I82371EB
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select SUPERIO_SMSC_SMSCSUPERIO
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select ROMCC
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_256
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config MAINBOARD_DIR
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string
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default nokia/ip530
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depends on BOARD_NOKIA_IP530
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config MAINBOARD_PART_NUMBER
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string
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default "IP530"
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depends on BOARD_NOKIA_IP530
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_NOKIA_IP530
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config IRQ_SLOT_COUNT
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int
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default 6
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depends on BOARD_NOKIA_IP530
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,94 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 3f0.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.5 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.9 on # Game port
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io 0x60 = 0x201
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end
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device pnp 3f0.a on # Power-management events (PME)
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io 0x60 = 0x600
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end
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device pnp 3f0.b on # MIDI port (MPU-401)
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io 0x60 = 0x330
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irq 0x70 = 5
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end
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
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device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
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device pci 0f.0 on end # CardBus bridge (TI PCI1225)
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device pci 0f.1 on end # CardBus bridge (TI PCI1225)
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end
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device pci_domain 1 on # PCI domain 1
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device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
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end
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device pci_domain 2 on # PCI domain 2
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device pci 04.0 on end # NIC (DECchip 21142/43)
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device pci 04.0 on end # NIC (DECchip 21142/43)
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end
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end
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||||
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||||
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
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* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x07 << 3) | 0x0, /* Interrupt router dev */
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0, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x122e, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x36, /* Checksum */
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
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{0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
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{0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
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{0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
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{0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
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{0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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||||||
|
*
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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||||||
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*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("Nokia IP530 Mainboard")
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};
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@ -0,0 +1,70 @@
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/*
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||||||
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* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
|
||||||
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*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
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||||||
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|
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#include <stdint.h>
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||||||
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#include <device/pci_def.h>
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||||||
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#include <arch/io.h>
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||||||
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#include <device/pnp_def.h>
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||||||
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#include <arch/romcc_io.h>
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||||||
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#include <arch/hlt.h>
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||||||
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#include <stdlib.h>
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||||||
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#include "pc80/serial.c"
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||||||
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#include "console/console.c"
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||||||
|
#include "lib/ramtest.c"
|
||||||
|
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
|
||||||
|
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
|
||||||
|
#include "northbridge/intel/i440bx/raminit.h"
|
||||||
|
#include "lib/debug.c"
|
||||||
|
#include "pc80/udelay_io.c"
|
||||||
|
#include "lib/delay.c"
|
||||||
|
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||||
|
#include "cpu/x86/bist.h"
|
||||||
|
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
|
||||||
|
|
||||||
|
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
|
||||||
|
|
||||||
|
static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||||
|
{
|
||||||
|
return smbus_read_byte(device, address);
|
||||||
|
}
|
||||||
|
|
||||||
|
#include "northbridge/intel/i440bx/raminit.c"
|
||||||
|
#include "northbridge/intel/i440bx/debug.c"
|
||||||
|
|
||||||
|
static void main(unsigned long bist)
|
||||||
|
{
|
||||||
|
if (bist == 0)
|
||||||
|
early_mtrr_init();
|
||||||
|
|
||||||
|
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
report_bist_failure(bist);
|
||||||
|
|
||||||
|
/* Enable access to the full ROM chip, needed very early by CBFS. */
|
||||||
|
i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
|
||||||
|
|
||||||
|
enable_smbus();
|
||||||
|
/* dump_spd_registers(); */
|
||||||
|
sdram_set_registers();
|
||||||
|
sdram_set_spd_registers();
|
||||||
|
sdram_enable();
|
||||||
|
/* ram_check(0, 640 * 1024); */
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue