Indent-based + manual cleanups for CN700 (trivial). As this will be ported
to v3 sooner or later we cleanup _now_, so we don't have to do it twice. - Whitespace, coding style improvements. - Fix a few typos. - Add a missing #endif in raminit.h. - Drop an unused variable. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
c1d06b782f
commit
ea7b518ec0
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@ -32,24 +32,27 @@
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static void agp_init(device_t dev)
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{
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u32 reg32;
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/* Some of this may not be necessary,
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* it should be handled by the OS */
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/* Some of this may not be necessary (should be handled by the OS). */
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printk_debug("Enabling AGP.\n");
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/* Allow R/W access to AGP registers */
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/* Allow R/W access to AGP registers. */
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pci_write_config8(dev, 0x4d, 0x15);
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/* Setup PCI latency timer */
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/* Setup PCI latency timer. */
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pci_write_config8(dev, 0xd, 0x8);
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/* Set to AGP 3.0 Mode, which should theoretically render the rest of
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* the registers set here pointless */
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/*
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* Set to AGP 3.0 Mode, which should theoretically render the rest of
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* the registers set here pointless.
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*/
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pci_write_config8(dev, 0x84, 0xb);
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/* AGP Request Queue Size */
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pci_write_config8(dev, 0x4a, 0x1f);
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/* AGP Hardware Support (default 0xc4)
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/*
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* AGP Hardware Support (default 0xc4)
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* 7: AGP SBA Enable (1 to Enable)
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* 6: AGP Enable
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* 5: Reserved
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@ -57,25 +60,26 @@ static void agp_init(device_t dev)
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* 3: AGP8X Mode Enable
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* 2: AGP4X Mode Enable
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* 1: AGP2X Mode Enable
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* 0: AGP1X Mode Enable */
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* 0: AGP1X Mode Enable
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*/
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pci_write_config8(dev, 0x4b, 0xc4);
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/* Enable AGP Backdoor */
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pci_write_config8(dev, 0xb5, 0x03);
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/* Set aperture to 32MB */
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/* TODO: Use config option, explain how it works */
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/* Set aperture to 32 MB. */
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/* TODO: Use config option, explain how it works. */
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pci_write_config32(dev, 0x94, 0x00010f38);
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/* Set GART Table Base Address (31:12) */
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/* Set GART Table Base Address (31:12). */
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pci_write_config32(dev, 0x98, (0x1558 << 12));
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/* Set AGP Aperture Base */
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/* Set AGP Aperture Base. */
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pci_write_config32(dev, 0x10, 0xf8000008);
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/* Enable CPU/PMSTR GART Access */
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/* Enable CPU/PMSTR GART Access. */
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reg32 = pci_read_config8(dev, 0xbf);
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reg32 |= 0x80;
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pci_write_config8(dev, 0xbf, reg32);
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/* Enable AGP Aperture. */
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reg32 = pci_read_config32(dev, 0x94);
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reg32 |= (3 << 7);
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@ -84,16 +88,17 @@ static void agp_init(device_t dev)
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/* AGP Control */
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pci_write_config8(dev, 0xbc, 0x21);
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pci_write_config8(dev, 0xbd, 0xd2);
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/* AGP Pad, driving strength, and delay control */
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/* All this should be constant, seeing as the
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* VGA controller is onboard */
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/*
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* AGP Pad, driving strength, and delay control. All this should be
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* constant, seeing as the VGA controller is onboard.
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*/
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pci_write_config8(dev, 0x40, 0xc7);
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pci_write_config8(dev, 0x41, 0xdb);
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pci_write_config8(dev, 0x42, 0x10);
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pci_write_config8(dev, 0x43, 0xdb);
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pci_write_config8(dev, 0x44, 0x24);
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/* AGPC CKG Control */
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pci_write_config8(dev, 0xc0, 0x02);
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pci_write_config8(dev, 0xc1, 0x02);
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@ -108,27 +113,30 @@ static const struct device_operations agp_operations = {
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};
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static const struct pci_driver agp_driver __pci_driver = {
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.ops = &agp_operations,
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.ops = &agp_operations,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_CN700_AGP,
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};
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/* This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
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config in this device takes presidence. We configure both just to be safe. */
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/*
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* This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
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* config in this device takes presidence. We configure both just to be safe.
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*/
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static void agp_bridge_init(device_t dev)
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{
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printk_debug("Setting up AGP Bridge device\n");
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printk_debug("Setting up AGP bridge device\n");
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pci_write_config16(dev, 0x4, 0x0007);
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/* Secondary Bus Number */
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pci_write_config8(dev, 0x19, 0x01);
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/* Subordinate Bus Number */
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pci_write_config8(dev, 0x1a, 0x01);
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/* IO Base */
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/* I/O Base */
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pci_write_config8(dev, 0x1c, 0xd0);
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/* IO Limit */
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/* I/O Limit */
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pci_write_config8(dev, 0x1d, 0xd0);
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/* Memory Base */
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pci_write_config16(dev, 0x20, 0xfb00);
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/* Memory Limit */
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@ -159,7 +167,7 @@ static const struct device_operations agp_bridge_operations = {
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};
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static const struct pci_driver agp_bridge_driver __pci_driver = {
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.ops = &agp_bridge_operations,
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.ops = &agp_bridge_operations,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_CN700_BRIDGE,
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};
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@ -18,8 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_via_cn700_config
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{
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struct northbridge_via_cn700_config {
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};
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extern struct chip_operations northbridge_via_cn700_ops;
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@ -19,18 +19,20 @@
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*/
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#ifndef __ROMCC__
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static void cn700_noop(){}
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static void cn700_noop()
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{
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}
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#endif
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/* VGA stuff */
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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#define SR_INDEX 0x3c4
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#define SR_DATA 0x3c5
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#define CRTM_INDEX 0x3b4
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#define CRTM_DATA 0x3b5
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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/* Memory Controller Registers */
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/* Memory controller registers */
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#define RANK0_END 0x40
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#define RANK1_END 0x41
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#define RANK2_END 0x42
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@ -45,7 +47,7 @@ static void cn700_noop(){}
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#define CH_A_DQS_OUTPUT_DELAY 0x70
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#define CH_A_MD_OUTPUT_DELAY 0x71
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/* RAM Init Commands */
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/* RAM init commands */
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#define RAM_COMMAND_NORMAL 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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@ -38,17 +38,15 @@ static void memctrl_init(device_t dev)
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{
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device_t vlink_dev;
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u16 reg16;
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u8 ranks;
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u8 pagec, paged, pagee, pagef;
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u8 shadowreg;
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/* Set up the vga framebuffer size */
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u8 ranks, pagec, paged, pagee, pagef, shadowreg;
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/* Set up the VGA framebuffer size. */
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reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
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pci_write_config16(dev, 0xa0, reg16);
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/* Set up VGA timers */
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/* Set up VGA timers. */
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pci_write_config8(dev, 0xa2, 0x44);
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for (ranks = 0x4b; ranks >= 0x48; ranks--) {
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if (pci_read_config8(dev, ranks)) {
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ranks -= 0x48;
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@ -64,7 +62,7 @@ static void memctrl_init(device_t dev)
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/* AGPCINT Misc. */
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pci_write_config8(dev, 0xb8, 0x08);
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/* shadown ram */
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/* Shadow RAM */
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pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
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/* PAGE C, D, E are all read write enable */
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pci_write_config8(dev, 0x80, pagec);
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@ -75,11 +73,13 @@ static void memctrl_init(device_t dev)
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shadowreg |= pagef;
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pci_write_config8(dev, 0x83, shadowreg);
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/* vlink mirror */
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vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
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vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
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if (vlink_dev) {
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pci_write_config8(vlink_dev, 0x61, pagec);
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pci_write_config8(vlink_dev, 0x62, paged);
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pci_write_config8(vlink_dev, 0x64, pagee);
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shadowreg = pci_read_config8(vlink_dev, 0x63);
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shadowreg |= pagef;
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pci_write_config8(vlink_dev, 0x63, shadowreg);
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@ -88,91 +88,93 @@ static void memctrl_init(device_t dev)
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static const struct device_operations memctrl_operations = {
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.read_resources = cn700_noop,
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.init = memctrl_init,
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.init = memctrl_init,
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};
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static const struct pci_driver memctrl_driver __pci_driver = {
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.ops = &memctrl_operations,
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.ops = &memctrl_operations,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
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};
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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struct resource *resource;
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printk_spew("Entering cn700 pci_domain_read_resources.\n");
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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/* Initialize the system wide I/O space constraints. */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints. */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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printk_spew("Leaving cn700 pci_domain_read_resources.\n");
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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if (!sizek)
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return;
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resource = new_resource(dev, index);
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resource->base = ((resource_t) basek) << 10;
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resource->size = ((resource_t) sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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if (!best || (best->base > new->base))
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best = new;
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}
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*best_p = best;
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}
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static u32 find_pci_tolm(struct bus *bus)
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{
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print_debug("Entering find_pci_tolm\n");
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struct resource *min;
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u32 tolm;
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print_debug("Entering find_pci_tolm\n");
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
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tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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if (min && tolm > min->base)
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tolm = min->base;
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}
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print_debug("Leaving find_pci_tolm\n");
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return tolm;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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/*
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* the order is important to find the correct ram size.
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*/
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static const u8 ramregs[] = {0x43, 0x42, 0x41, 0x40};
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/* The order is important to find the correct RAM size. */
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static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
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device_t mc_dev;
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u32 pci_tolm;
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u32 pci_tolm;
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printk_spew("Entering cn700 pci_domain_set_resources.\n");
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
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if (mc_dev) {
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unsigned long tomk, tolmk;
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@ -180,30 +182,30 @@ static void pci_domain_set_resources(device_t dev)
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int i, idx;
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/*
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* once the register value is not zero, the ramsize is
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* this register's value multiply 64 * 1024 * 1024
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* Once the register value is not zero, the RAM size is
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* this register's value multiply 64 * 1024 * 1024.
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*/
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for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
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unsigned char reg;
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for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
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rambits = pci_read_config8(mc_dev, ramregs[i]);
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if (rambits != 0)
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break;
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}
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tomk = rambits * 64 * 1024;
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printk_spew("tomk is 0x%x\n", tomk);
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/* Compute the Top Of Low Memory, in Kb */
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/* Compute the Top Of Low Memory (TOLM), in Kb. */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does does not overlap the memory. */
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tolmk = tomk;
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}
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/* Report the memory regions */
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/* Report the memory regions. */
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idx = 10;
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/* TODO: Hole needed? */
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ram_resource(dev, idx++, 0, 640); /* first 640k */
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/* Leave a hole for vga, 0xa0000 - 0xc0000 */
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ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
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ram_resource(dev, idx++, 0, 640); /* First 640k */
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/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
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ram_resource(dev, idx++, 768,
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(tolmk - 768 - CONFIG_VIDEO_MB * 1024));
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}
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assign_resources(&dev->link[0]);
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}
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@ -212,21 +214,21 @@ static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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printk_debug("Entering cn700 pci_domain_scan_bus.\n");
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static const struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
initialize_cpus(&dev->link[0]);
|
||||
initialize_cpus(&dev->link[0]);
|
||||
}
|
||||
|
||||
static void cpu_bus_noop(device_t dev)
|
||||
|
|
@ -234,25 +236,24 @@ static void cpu_bus_noop(device_t dev)
|
|||
}
|
||||
|
||||
static const struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_noop,
|
||||
.set_resources = cpu_bus_noop,
|
||||
.enable_resources = cpu_bus_noop,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
.read_resources = cpu_bus_noop,
|
||||
.set_resources = cpu_bus_noop,
|
||||
.enable_resources = cpu_bus_noop,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
printk_spew("In cn700 enable_dev for device %s.\n", dev_path(dev));
|
||||
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
/* Set the operations if it is a special bus type. */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
pci_set_method(dev);
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_via_cn700_ops = {
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <delay.h>
|
||||
#include "cn700.h"
|
||||
|
||||
//#define DEBUG_RAM_SETUP 1
|
||||
// #define DEBUG_RAM_SETUP 1
|
||||
|
||||
#ifdef DEBUG_RAM_SETUP
|
||||
#define PRINT_DEBUG_MEM(x) print_debug(x)
|
||||
|
|
@ -60,16 +60,16 @@ static void do_ram_command(device_t dev, u8 command)
|
|||
}
|
||||
|
||||
/**
|
||||
* Configure the bus between the cpu and the northbridge. This might be able to
|
||||
* Configure the bus between the CPU and the northbridge. This might be able to
|
||||
* be moved to post-ram code in the future. For the most part, these registers
|
||||
* should not be messed around with. These are too complex to explain short of
|
||||
* copying the datasheets into the comments, but most of these values are from
|
||||
* the BIOS Porting Guide, so they should work on any board. If they don't,
|
||||
* try the values from your factory BIOS.
|
||||
*
|
||||
* TODO: Changing the DRAM frequency doesn't work (hard lockup)
|
||||
* TODO: Changing the DRAM frequency doesn't work (hard lockup).
|
||||
*
|
||||
* @param dev The northbridge's CPU Host Interface (D0F2)
|
||||
* @param dev The northbridge's CPU Host Interface (D0F2).
|
||||
*/
|
||||
static void c7_cpu_setup(device_t dev)
|
||||
{
|
||||
|
|
@ -87,13 +87,15 @@ static void c7_cpu_setup(device_t dev)
|
|||
/* Write Policy */
|
||||
pci_write_config8(dev, 0x56, 0x01);
|
||||
/* Miscellaneous Control */
|
||||
/* DRAM Operating Frequency (Bits 7:5)
|
||||
* 000 : 100MHz 001 : 133MHz
|
||||
* 010 : 166MHz 011 : 200MHz
|
||||
* 100 : 266MHz 101 : 333MHz
|
||||
* 110/111 : Reserved */
|
||||
/*
|
||||
* DRAM Operating Frequency (bits 7:5)
|
||||
* 000 : 100MHz 001 : 133MHz
|
||||
* 010 : 166MHz 011 : 200MHz
|
||||
* 100 : 266MHz 101 : 333MHz
|
||||
* 110/111 : Reserved
|
||||
*/
|
||||
/* CPU Miscellaneous Control */
|
||||
pci_write_config8(dev, 0x59, 0x44);
|
||||
pci_write_config8(dev, 0x59, 0x44);
|
||||
/* Write Policy */
|
||||
pci_write_config8(dev, 0x5d, 0xb2);
|
||||
/* Bandwidth Timer */
|
||||
|
|
@ -112,8 +114,8 @@ static void c7_cpu_setup(device_t dev)
|
|||
/* Read Line Burst DRDY# Timing Control */
|
||||
pci_write_config8(dev, 0x66, 0xff);
|
||||
pci_write_config8(dev, 0x67, 0x30);
|
||||
|
||||
/* Host Bus IO Circuit (See datasheet) */
|
||||
|
||||
/* Host Bus I/O Circuit (see datasheet) */
|
||||
/* Host Address Pullup/down Driving */
|
||||
pci_write_config8(dev, 0x70, 0x11);
|
||||
pci_write_config8(dev, 0x71, 0x11);
|
||||
|
|
@ -133,7 +135,7 @@ static void c7_cpu_setup(device_t dev)
|
|||
pci_write_config8(dev, 0x79, 0xaa);
|
||||
/* Address Strobe Input Delay Control */
|
||||
pci_write_config8(dev, 0x7a, 0x24);
|
||||
// Address CKG Rising/Falling Time Control
|
||||
/* Address CKG Rising/Falling Time Control */
|
||||
pci_write_config8(dev, 0x7b, 0xaa);
|
||||
/* Address CKG Clock Rising/Falling Time Control */
|
||||
pci_write_config8(dev, 0x7c, 0x00);
|
||||
|
|
@ -148,10 +150,10 @@ static void c7_cpu_setup(device_t dev)
|
|||
}
|
||||
|
||||
/**
|
||||
* Set up dram size according to spd data. Eventually, DRAM timings should be
|
||||
* Set up DRAM size according to SPD data. Eventually, DRAM timings should be
|
||||
* done in a similar manner.
|
||||
*
|
||||
* @param ctrl The northbridge devices and spd addresses.
|
||||
* @param ctrl The northbridge devices and SPD addresses.
|
||||
*/
|
||||
static void sdram_set_size(const struct mem_controller *ctrl)
|
||||
{
|
||||
|
|
@ -159,37 +161,37 @@ static void sdram_set_size(const struct mem_controller *ctrl)
|
|||
|
||||
ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS);
|
||||
ranks = (ranks & 0x07) + 1;
|
||||
density = spd_read_byte(ctrl->channel0[0], SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
|
||||
switch (density)
|
||||
{
|
||||
case 0x80:
|
||||
result = 0x08; /* 512MB / 64MB = 0x08 */
|
||||
break;
|
||||
case 0x40:
|
||||
result = 0x04;
|
||||
break;
|
||||
case 0x20:
|
||||
result = 0x02;
|
||||
break;
|
||||
case 0x10:
|
||||
result = 0xff; /* 16GB */
|
||||
break;
|
||||
case 0x08:
|
||||
result = 0xff; /* 8GB */
|
||||
break;
|
||||
case 0x04:
|
||||
result = 0xff; /* 4GB */
|
||||
break;
|
||||
case 0x02:
|
||||
result = 0x20; /* 2GB */
|
||||
break;
|
||||
case 0x01:
|
||||
result = 0x10; /* 1GB */
|
||||
break;
|
||||
density = spd_read_byte(ctrl->channel0[0],
|
||||
SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
|
||||
switch (density) {
|
||||
case 0x80:
|
||||
result = 0x08; /* 512MB / 64MB = 0x08 */
|
||||
break;
|
||||
case 0x40:
|
||||
result = 0x04;
|
||||
break;
|
||||
case 0x20:
|
||||
result = 0x02;
|
||||
break;
|
||||
case 0x10:
|
||||
result = 0xff; /* 16GB */
|
||||
break;
|
||||
case 0x08:
|
||||
result = 0xff; /* 8GB */
|
||||
break;
|
||||
case 0x04:
|
||||
result = 0xff; /* 4GB */
|
||||
break;
|
||||
case 0x02:
|
||||
result = 0x20; /* 2GB */
|
||||
break;
|
||||
case 0x01:
|
||||
result = 0x10; /* 1GB */
|
||||
break;
|
||||
}
|
||||
|
||||
if (result == 0xff)
|
||||
die("dram module size too big, not supported by cn700\r\n");
|
||||
die("DRAM module size too big, not supported by CN700\r\n");
|
||||
|
||||
pci_write_config8(ctrl->d0f3, 0x40, result);
|
||||
pci_write_config8(ctrl->d0f3, 0x48, 0x00);
|
||||
|
|
@ -197,7 +199,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
|
|||
pci_write_config8(ctrl->d0f3, 0x41, result * ranks);
|
||||
pci_write_config8(ctrl->d0f3, 0x49, result);
|
||||
}
|
||||
/* size mirror */
|
||||
/* Size mirror */
|
||||
pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2);
|
||||
pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2);
|
||||
/* Low Top Address */
|
||||
|
|
@ -207,55 +209,53 @@ static void sdram_set_size(const struct mem_controller *ctrl)
|
|||
|
||||
/* Physical-Virtual Mapping */
|
||||
if (ranks == 2)
|
||||
pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
|
||||
pci_write_config8(ctrl->d0f3, 0x54,
|
||||
1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
|
||||
if (ranks == 1)
|
||||
pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4);
|
||||
pci_write_config8(ctrl->d0f3, 0x55, 0x00);
|
||||
/* virtual rank interleave, disable */
|
||||
/* Virtual rank interleave, disable */
|
||||
pci_write_config32(ctrl->d0f3, 0x58, 0x00);
|
||||
|
||||
/* MA Map Type */
|
||||
result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
|
||||
if (result == 8) {
|
||||
col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
|
||||
switch (col)
|
||||
{
|
||||
case 10:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
|
||||
break;
|
||||
case 11:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
|
||||
break;
|
||||
case 12:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
|
||||
break;
|
||||
switch (col) {
|
||||
case 10:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
|
||||
break;
|
||||
case 11:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
|
||||
break;
|
||||
case 12:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (result == 4) {
|
||||
} else if (result == 4) {
|
||||
col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
|
||||
switch (col)
|
||||
{
|
||||
case 9:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x00);
|
||||
break;
|
||||
case 10:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x20);
|
||||
break;
|
||||
case 11:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x40);
|
||||
break;
|
||||
case 12:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x60);
|
||||
break;
|
||||
switch (col) {
|
||||
case 9:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x00);
|
||||
break;
|
||||
case 10:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x20);
|
||||
break;
|
||||
case 11:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x40);
|
||||
break;
|
||||
case 12:
|
||||
pci_write_config8(ctrl->d0f3, 0x50, 0x60);
|
||||
break;
|
||||
}
|
||||
}
|
||||
pci_write_config8(ctrl->d0f3, 0x51, 0x00);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set up various ram and other control registers statically. Some of these may
|
||||
* not be needed, other should be done with spd info, but that's a project for
|
||||
* the future
|
||||
* Set up various RAM and other control registers statically. Some of these may
|
||||
* not be needed, other should be done with SPD info, but that's a project for
|
||||
* the future.
|
||||
*/
|
||||
static void sdram_set_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
|
|
@ -265,48 +265,49 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
pci_write_config8(ctrl->d0f3, 0x61, 0xe0);
|
||||
/* Set CAS=4 */
|
||||
pci_write_config8(ctrl->d0f3, 0x62, 0xfa);
|
||||
/* dram timing-3 */
|
||||
/* DRAM timing-3 */
|
||||
pci_write_config8(ctrl->d0f3, 0x63, 0xca);
|
||||
/* dram timing-4 */
|
||||
/* DRAM timing-4 */
|
||||
pci_write_config8(ctrl->d0f3, 0x64, 0xcc);
|
||||
/* DIMM command / Address Selection */
|
||||
pci_write_config8(ctrl->d0f3, 0x67, 0x00);
|
||||
/* Disable cross bank/multi page mode */
|
||||
pci_write_config8(ctrl->d0f3, 0x69, 0x00);
|
||||
/* disable refresh now */
|
||||
/* Disable refresh now */
|
||||
pci_write_config8(ctrl->d0f3, 0x6a, 0x00);
|
||||
|
||||
/* frequency 100MHZ */
|
||||
/* Frequency 100 MHz */
|
||||
pci_write_config8(ctrl->d0f3, 0x90, 0x00);
|
||||
pci_write_config8(ctrl->d0f2, 0x57, 0x18);
|
||||
/* Allow manual dll reset */
|
||||
/* Allow manual DLL reset */
|
||||
pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
|
||||
|
||||
/* Bank/Rank Interleave Address Select */
|
||||
pci_write_config8(ctrl->d0f3, 0x52, 0x33);
|
||||
pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
|
||||
|
||||
/* Set to DDR2 sdram, BL=8 (0xc8, 0xc0 for bl=4) */
|
||||
|
||||
/* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */
|
||||
pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
|
||||
|
||||
/* DRAM Bus Turn-Around Setting */
|
||||
pci_write_config8(ctrl->d0f3, 0x60, 0x03);
|
||||
/* DRAM Arbitration Control */
|
||||
pci_write_config8(ctrl->d0f3, 0x66, 0x80);
|
||||
/* DQS Tuning: testing on a couple different boards has shown this is
|
||||
/*
|
||||
* DQS Tuning: testing on a couple different boards has shown this is
|
||||
* static, or close enough that it can be. Which is good, because the
|
||||
* tuning function used too many registers
|
||||
* tuning function used too many registers.
|
||||
*/
|
||||
/* DQS Output Delay for CHannel A */
|
||||
/* DQS Output Delay for Channel A */
|
||||
pci_write_config8(ctrl->d0f3, 0x70, 0x00);
|
||||
/* MD Output Delay for Channel A */
|
||||
pci_write_config8(ctrl->d0f3, 0x71, 0x01);
|
||||
pci_write_config8(ctrl->d0f3, 0x73, 0x01);
|
||||
|
||||
/* dram arbitration timer */
|
||||
/* DRAM arbitration timer */
|
||||
pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
|
||||
|
||||
/* dram signal timing control */
|
||||
/* DRAM signal timing control */
|
||||
pci_write_config8(ctrl->d0f3, 0x74, 0x01);
|
||||
pci_write_config8(ctrl->d0f3, 0x75, 0x01);
|
||||
pci_write_config8(ctrl->d0f3, 0x76, 0x06);
|
||||
|
|
@ -316,7 +317,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
|
||||
pci_write_config8(ctrl->d0f3, 0x7b, 0x10);
|
||||
|
||||
/* dram clocking control */
|
||||
/* DRAM clocking control */
|
||||
pci_write_config8(ctrl->d0f3, 0x91, 0x01);
|
||||
/* CS/CKE Clock Phase Control */
|
||||
pci_write_config8(ctrl->d0f3, 0x92, 0x02);
|
||||
|
|
@ -325,18 +326,18 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
/* DCLKO Feedback Mode Output Control */
|
||||
pci_write_config8(ctrl->d0f3, 0x94, 0x00);
|
||||
pci_write_config8(ctrl->d0f3, 0x9d, 0x0f);
|
||||
|
||||
|
||||
/* SDRAM ODT Control */
|
||||
pci_write_config8(ctrl->d0f3, 0xda, 0x80);
|
||||
/* Channel A DQ/DQS CKG Output Delay Control */
|
||||
pci_write_config8(ctrl->d0f3, 0xdc, 0x54);
|
||||
/* Channel A DQ/DQS CKG Output Delay Control */
|
||||
pci_write_config8(ctrl->d0f3, 0xdd, 0x55);
|
||||
/* odt lookup table */
|
||||
/* ODT lookup table */
|
||||
pci_write_config8(ctrl->d0f3, 0xd8, 0x01);
|
||||
pci_write_config8(ctrl->d0f3, 0xd9, 0x0a);
|
||||
|
||||
/* ddr sdram control */
|
||||
/* DDR SDRAM control */
|
||||
pci_write_config8(ctrl->d0f3, 0x6d, 0xc0);
|
||||
pci_write_config8(ctrl->d0f3, 0x6f, 0x41);
|
||||
|
||||
|
|
@ -344,7 +345,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
pci_write_config8(ctrl->d0f3, 0xd0, 0xaa);
|
||||
|
||||
/* Compensation Control */
|
||||
pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /*enable auto compensation*/
|
||||
pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /* Enable autocompensation */
|
||||
/* ODT (some are set with driving select above) */
|
||||
pci_write_config8(ctrl->d0f3, 0xd4, 0x80);
|
||||
pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
|
||||
|
|
@ -362,8 +363,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
pci_write_config8(ctrl->d0f3, 0xee, 0x00);
|
||||
/* DQS CKG Input Delay Control */
|
||||
pci_write_config8(ctrl->d0f3, 0xef, 0x10);
|
||||
|
||||
/* dram duty control */
|
||||
|
||||
/* DRAM duty control */
|
||||
pci_write_config8(ctrl->d0f3, 0xed, 0x10);
|
||||
|
||||
/* SMM and APIC decoding, we do not use SMM */
|
||||
|
|
@ -372,23 +373,23 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
|
|||
/* SMM and APIC decoding mirror */
|
||||
pci_write_config8(ctrl->d0f7, 0xe6, reg);
|
||||
|
||||
/* dram module configuration */
|
||||
/* DRAM module configuration */
|
||||
pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
|
||||
}
|
||||
|
||||
static void sdram_set_post(const struct mem_controller *ctrl)
|
||||
{
|
||||
device_t dev = ctrl->d0f3;
|
||||
|
||||
/* Enable multipage mode. */
|
||||
pci_write_config8(dev, 0x69, 0x03);
|
||||
|
||||
/* Enable refresh. */
|
||||
pci_write_config8(dev, 0x6a, 0x32);
|
||||
|
||||
// vga device
|
||||
pci_write_config16(dev, 0xa0, (1 <<15));
|
||||
/* VGA device. */
|
||||
pci_write_config16(dev, 0xa0, (1 << 15));
|
||||
pci_write_config16(dev, 0xa4, 0x0010);
|
||||
|
||||
}
|
||||
|
||||
static void sdram_enable(device_t dev, unsigned long rank_address)
|
||||
|
|
@ -410,33 +411,35 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
|
|||
/* 3. Mode register set. */
|
||||
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
|
||||
do_ram_command(dev, RAM_COMMAND_MRS);
|
||||
read32(rank_address + 0x120000);// EMRS DLL Enable
|
||||
read32(rank_address + 0x800); // MRS DLL Reset
|
||||
|
||||
read32(rank_address + 0x120000); /* EMRS DLL Enable */
|
||||
read32(rank_address + 0x800); /* MRS DLL Reset */
|
||||
|
||||
/* 4. Precharge all again. */
|
||||
PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
|
||||
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
|
||||
read32(rank_address + 0x0);
|
||||
|
||||
|
||||
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
|
||||
PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
|
||||
do_ram_command(dev, RAM_COMMAND_CBR);
|
||||
for(i = 0; i < 8; i++) {
|
||||
for (i = 0; i < 8; i++) {
|
||||
read32(rank_address + 0x20);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* 6. Mode register set. */
|
||||
PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
|
||||
//safe value for now, BL=8, WR=5, CAS=4
|
||||
/* (E)MRS values are from the BPG. No direct explanation is given, but
|
||||
/* Safe value for now, BL=8, WR=5, CAS=4 */
|
||||
/*
|
||||
* (E)MRS values are from the BPG. No direct explanation is given, but
|
||||
* they should somehow conform to the JEDEC DDR2 SDRAM Specification
|
||||
* (JESD79-2C). */
|
||||
* (JESD79-2C).
|
||||
*/
|
||||
do_ram_command(dev, RAM_COMMAND_MRS);
|
||||
read32(rank_address + 0x002258); // MRS command
|
||||
read32(rank_address + 0x121c20); // EMRS OCD Default
|
||||
read32(rank_address + 0x120020); // EMRS OCD Calibration Mode Exit
|
||||
|
||||
read32(rank_address + 0x002258); /* MRS command */
|
||||
read32(rank_address + 0x121c20); /* EMRS OCD Default */
|
||||
read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
|
||||
|
||||
/* 8. Normal operation */
|
||||
PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
|
||||
do_ram_command(dev, RAM_COMMAND_NORMAL);
|
||||
|
|
@ -444,7 +447,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
|
|||
}
|
||||
|
||||
/*
|
||||
* Support one dimm with up to 2 ranks
|
||||
* Support one DIMM with up to 2 ranks.
|
||||
*/
|
||||
static void ddr_ram_setup(const struct mem_controller *ctrl)
|
||||
{
|
||||
|
|
@ -456,7 +459,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
|
|||
sdram_enable(ctrl->d0f3, 0);
|
||||
reg = pci_read_config8(ctrl->d0f3, 0x41);
|
||||
if (reg != 0)
|
||||
sdram_enable(ctrl->d0f3, pci_read_config8(ctrl->d0f3, 0x40) << 26);
|
||||
sdram_enable(ctrl->d0f3,
|
||||
pci_read_config8(ctrl->d0f3, 0x40) << 26);
|
||||
sdram_set_post(ctrl);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -21,9 +21,11 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 1 //Only one works, for now.
|
||||
#define DIMM_SOCKETS 1 /* Only one works, for now. */
|
||||
|
||||
struct mem_controller {
|
||||
device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0;
|
||||
u8 channel0[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -18,8 +18,10 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Note: Some of the VGA control registers are located on the memory controller.
|
||||
Registers are set both in raminit.c and northbridge.c */
|
||||
/*
|
||||
* Note: Some of the VGA control registers are located on the memory
|
||||
* controller. Registers are set both in raminit.c and northbridge.c.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
|
|
@ -37,75 +39,74 @@
|
|||
|
||||
void write_protect_vgabios(void)
|
||||
{
|
||||
//Don't bother for now
|
||||
/* Don't bother for now. */
|
||||
}
|
||||
|
||||
static void vga_init(device_t dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
print_debug("Copying BOCHS Bios to 0xf000\n");
|
||||
/* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
|
||||
* This is for compatibility with the VGA ROM's BIOS callbacks */
|
||||
print_debug("Copying BOCHS BIOS to 0xf000\n");
|
||||
/*
|
||||
* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
|
||||
* This is for compatibility with the VGA ROM's BIOS callbacks.
|
||||
*/
|
||||
memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
|
||||
|
||||
printk_debug("Initializing VGA\n");
|
||||
|
||||
/* Set memory rate to 200MHz */
|
||||
|
||||
/* Set memory rate to 200 MHz. */
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
reg8 = inb(CRTM_DATA);
|
||||
reg8 &= 0x0f;
|
||||
reg8 |= (0x1 << 4);
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
outb(reg8, CRTM_DATA);
|
||||
|
||||
/* Set framebuffer size */
|
||||
|
||||
/* Set framebuffer size. */
|
||||
reg8 = (CONFIG_VIDEO_MB / 4);
|
||||
outb(0x39, SR_INDEX);
|
||||
outb(reg8, SR_DATA);
|
||||
|
||||
|
||||
|
||||
pci_write_config8(dev, 0x04, 0x07);
|
||||
pci_write_config8(dev, 0x0d, 0x20);
|
||||
pci_write_config32(dev,0x10, 0xf4000008);
|
||||
pci_write_config32(dev,0x14, 0xfb000000);
|
||||
|
||||
|
||||
pci_write_config32(dev, 0x10, 0xf4000008);
|
||||
pci_write_config32(dev, 0x14, 0xfb000000);
|
||||
|
||||
printk_debug("INSTALL REAL-MODE IDT\n");
|
||||
setup_realmode_idt();
|
||||
printk_debug("DO THE VGA BIOS\n");
|
||||
do_vgabios();
|
||||
/* VGA seems to work without this, but crash & burn with it */
|
||||
//printk_debug("Enable VGA console\n");
|
||||
//vga_enable_console();
|
||||
/* VGA seems to work without this, but crash & burn with it. */
|
||||
// printk_debug("Enable VGA console\n");
|
||||
// vga_enable_console();
|
||||
|
||||
/* It's not clear if these need to be programmed before or after
|
||||
* the VGA bios runs. Try both, clean up later */
|
||||
/* Set memory rate to 200MHz */
|
||||
* the VGA BIOS runs. Try both, clean up later. */
|
||||
/* Set memory rate to 200 MHz (again). */
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
reg8 = inb(CRTM_DATA);
|
||||
reg8 &= 0x0f;
|
||||
reg8 |= (0x1 << 4);
|
||||
outb(0x3d, CRTM_INDEX);
|
||||
outb(reg8, CRTM_DATA);
|
||||
|
||||
/* Set framebuffer size (again) */
|
||||
|
||||
/* Set framebuffer size (again). */
|
||||
reg8 = (CONFIG_VIDEO_MB / 4);
|
||||
outb(0x39, SR_INDEX);
|
||||
outb(reg8, SR_DATA);
|
||||
|
||||
/* Clear the BOCHs Bios out of memory, so it doesn't confuse linux */
|
||||
/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
|
||||
memset(0xf0000, 0, 0x10000);
|
||||
}
|
||||
|
||||
static void vga_read_resources(device_t dev)
|
||||
{
|
||||
dev->rom_address = 0xfff80000;
|
||||
dev->on_mainboard=1;
|
||||
dev->on_mainboard = 1;
|
||||
pci_dev_read_resources(dev);
|
||||
}
|
||||
|
||||
|
||||
static const struct device_operations vga_operations = {
|
||||
.read_resources = vga_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
|
|
@ -115,7 +116,7 @@ static const struct device_operations vga_operations = {
|
|||
};
|
||||
|
||||
static const struct pci_driver vga_driver __pci_driver = {
|
||||
.ops = &vga_operations,
|
||||
.ops = &vga_operations,
|
||||
.vendor = PCI_VENDOR_ID_VIA,
|
||||
.device = PCI_DEVICE_ID_VIA_CN700_VGA,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue