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fsp_model_406dx: use external microcode .h files for rangeley 

The microcode for the Rangeley chip is supplied as .h files in the
Rangeley FSP POSTGOLD4 package.

When the rangeley microcode gets put into the blobs directory, this
can be reverted and the binary file put into the makefile.

Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2015-11-05 09:00:20 -07:00
parent c4fa3fdd3e
commit ea7b636607
3 changed files with 9 additions and 15 deletions
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18
src/cpu/intel/fsp_model_406dx/Kconfig
View File

@ -33,6 +33,9 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER
# Microcode header files are delivered in FSP package
select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
choice choice
prompt "Rangeley CPU Stepping" prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0 default FSP_MODEL_406DX_B0
@ -53,16 +56,9 @@ config ENABLE_VMX
bool "Enable VMX for virtualization" bool "Enable VMX for virtualization"
default n default n
config HAVE_CPU_MICROCODE_FILE #set up microcode for rangeley POSTGOLD4 release
bool "Add microcode file" config CPU_MICROCODE_HEADER_FILES
help string
The microcode binary default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"
config CPU_MICROCODE_FILE
string "Path and filename of CPU microcode"
default "microcode.bin"
depends on HAVE_CPU_MICROCODE_FILE
help
The path and filename of the file containing the CPU microcode.
endif #CPU_INTEL_FSP_MODEL_406DX endif #CPU_INTEL_FSP_MODEL_406DX

3
src/cpu/intel/fsp_model_406dx/Makefile.inc
View File

@ -23,6 +23,3 @@ cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
endif endif
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
# We don't have microcode for this CPU
# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
# cpu_microcode_bins += ???

3
src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View File

@ -170,7 +170,8 @@ static void model_406dx_init(struct device *cpu)
x86_enable_cache(); x86_enable_cache();
/* Load microcode */ /* Load microcode */
intel_update_microcode_from_cbfs(); if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */ /* Clear out pending MCEs */
configure_mca(); configure_mca();