soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY`
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in `igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`. Nobody missed it for nearly a year, plus, it's not applied on the GOP path, let's drop it. Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -169,15 +169,6 @@ config PCR_BASE_ADDRESS
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help
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help
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This option allows you to select MMIO Base Address of sideband bus.
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This option allows you to select MMIO Base Address of sideband bus.
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config PRE_GRAPHICS_DELAY
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int "Graphics initialization delay in ms"
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default 0
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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config SERIAL_CPU_INIT
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config SERIAL_CPU_INIT
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bool
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bool
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default n
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default n
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@ -93,16 +93,6 @@ static void igd_init(struct device *dev)
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Wait for any configured pre-graphics delay */
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if (!acpi_is_wakeup_s3()) {
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#if IS_ENABLED(CONFIG_CHROMEOS)
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if (display_init_required() || vboot_wants_oprom())
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mdelay(CONFIG_PRE_GRAPHICS_DELAY);
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#else
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mdelay(CONFIG_PRE_GRAPHICS_DELAY);
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#endif
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}
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/* Initialize PCI device, load/execute BIOS Option ROM */
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/* Initialize PCI device, load/execute BIOS Option ROM */
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pci_dev_init(dev);
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pci_dev_init(dev);
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}
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}
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