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mb/intel/adlrvp_m: Enable LTR for PCIE

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BUG=none
TEST=Use command $ lspci -vv
     LTR+ is listed on DevCtl2

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bernardo Perez Priego 2021-05-17 17:37:29 -07:00 committed by Tim Wawrzynczak
parent de44c0cc36
commit ea8a6a2ba2
1 changed files with 8 additions and 4 deletions
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12
src/mainboard/intel/adlrvp/devicetree_m.cb
View file

@ -42,28 +42,32 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(4)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Enable PCH PCIE RP 5 using CLK 2
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Enable PCH PCIE RP 9 using CLK 3
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
#Enable PCH PCIE RP 10 using CLK 1
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
.PcieRpL1Substates = L1_SS_L1_2,
}"
# Hybrid storage mode