soc/amd/stoneyridge/include: delete amd_pci_int_types.h
Due to review 20b8c821e4 being abandoned and review 376dc82dca
being
merged, file amd_pci_int_types.h became orphaned (not included by any
file), while an array similar to intr_types[] (but that also includes
the associated register index) was created in southbridge.c replacing
the original array functionality.
Remove the header amd_pci_int_types.h from the repository.
BUG=b:70328428
TEST=Build kahlee with no errors.
Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
parent
b3937bb108
commit
ea8de493ff
|
@ -1,37 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __AMD_PCI_INT_TYPES_H__
|
|
||||||
#define __AMD_PCI_INT_TYPES_H__
|
|
||||||
|
|
||||||
const char *intr_types[] = {
|
|
||||||
[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t",
|
|
||||||
"INTF#\t", "INTG#\t", "INTH#\t",
|
|
||||||
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA",
|
|
||||||
"Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
|
|
||||||
[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t",
|
|
||||||
"PerMon\t", "SD\t\t",
|
|
||||||
[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t",
|
|
||||||
"IMC INT4\t", "IMC INT5\t",
|
|
||||||
[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",
|
|
||||||
"Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
|
|
||||||
[0x7f] = "RSVD\t",
|
|
||||||
[0x40] = "IDE\t", "SATA\t",
|
|
||||||
[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
|
|
||||||
[0x62] = "GPIO\t",
|
|
||||||
[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* __AMD_PCI_INT_TYPES_H__ */
|
|
Loading…
Reference in New Issue