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mb/google/brox: Fix configuration for TPM 

On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to
reflect this.  Also, fixing up the TPM entry in the device tree.
Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Shelley Chen 2023-11-13 10:02:28 -08:00
parent 2d589cfc6c
commit ea9248e9fb
2 changed files with 16 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/brox/Kconfig
View File

@ -76,7 +76,7 @@ config DEVICETREE
config DRIVER_TPM_I2C_BUS
hex
default 0x1 if BOARD_GOOGLE_BROX
default 0x4 if BOARD_GOOGLE_BROX
config DRIVER_TPM_I2C_ADDR
hex
@ -87,7 +87,7 @@ config FMDFILE
config TPM_TIS_ACPI_INTERRUPT
int
default 13
default 66 # GPE0_DW2_02 (GPP_E2)
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

30
src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
View File

@ -76,14 +76,12 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio and WFC |
#| I2C1 | cr50 TPM. Early init is |
#| I2C0 | Trackpad |
#| I2C1 | Touchscreen |
#| I2C2 | ISH Sensor |
#| I2C4 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C2 | SAR0 |
#| I2C3 | Touchscreen |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
@ -94,24 +92,18 @@ chip soc/intel/alderlake
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 900,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[3] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[5] = {
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
@ -167,7 +159,13 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref i2c3 on end
device ref i2c4 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E2_IRQ)"
device i2c 50 on end
end
end
device ref heci1 on end
device ref sata on end
device ref pcie_rp8 on