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google/lars,lili: Set new thermal parameters 

Cherry-pick from Chromium:
55c0eb3 [Lili: Set new thermal parameters]

Set new parameters of DPTF for both Lars and Lili.
The acoustic will have higher 1.6dB in transition mode,
when using Lili fan table on Lars.

Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>

Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
david 2017-03-15 17:19:06 +08:00 committed by Martin Roth
parent 850df4d3dd
commit ea942169f9
1 changed files with 20 additions and 20 deletions
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40
src/mainboard/google/lars/acpi/dptf.asl
View File

@ -16,28 +16,28 @@
#define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_PASSIVE 94
#define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_CRITICAL 99
#define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_CPU_ACTIVE_AC1 70
#define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_ID 2
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" #define DPTF_TSR0_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR0_PASSIVE 66 #define DPTF_TSR0_PASSIVE 65
#define DPTF_TSR0_CRITICAL 71 #define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR0_ACTIVE_AC0 120 #define DPTF_TSR0_ACTIVE_AC0 60
#define DPTF_TSR0_ACTIVE_AC1 110 #define DPTF_TSR0_ACTIVE_AC1 48
#define DPTF_TSR0_ACTIVE_AC2 47 #define DPTF_TSR0_ACTIVE_AC2 42
#define DPTF_TSR0_ACTIVE_AC3 44 #define DPTF_TSR0_ACTIVE_AC3 39
#define DPTF_TSR0_ACTIVE_AC4 41 #define DPTF_TSR0_ACTIVE_AC4 36
#define DPTF_TSR0_ACTIVE_AC5 38 #define DPTF_TSR0_ACTIVE_AC5 34
#define DPTF_TSR0_ACTIVE_AC6 35 #define DPTF_TSR0_ACTIVE_AC6 32
#define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 75 #define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_ID 0
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR2_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_PASSIVE 65
#define DPTF_TSR2_CRITICAL 70 #define DPTF_TSR2_CRITICAL 70
@ -83,12 +83,12 @@ Name (DART, Package () {
* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
* AC7, AC8, AC9 * AC7, AC8, AC9
*/ */
\_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0, \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 0, 0, 0, 0, 0,
0, 0, 0 0, 0, 0
}, },
Package () { Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38, \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 90, 75, 62, 55, 47,
37, 0, 0, 0 41, 0, 0, 0
} }
}) })
#endif #endif