diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index ae2440daab..36884a1b1c 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -59,8 +59,8 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
 	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
 	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
 
-	wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
+	wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base);
+	wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask);
 }
 
 static void fill_in_relocation_params(struct smm_relocation_params *params)
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 3bf8301cfd..b8d15179e9 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -31,9 +31,10 @@
 #define IA32_SMRR_PHYS_MASK		0x1f3
 #define SMRR_PHYS_MASK_LOCK		(1 << 10)
 
-/* Specific to model_6fx and model_1067x */
-#define MSR_SMRR_PHYS_BASE		0xa0
-#define MSR_SMRR_PHYS_MASK		0xa1
+/* Specific to model_6fx and model_1067x.
+   These are named MSR_SMRR_PHYSBASE in the SDM. */
+#define CORE2_SMRR_PHYS_BASE		0xa0
+#define CORE2_SMRR_PHYS_MASK		0xa1
 
 #define MTRR_PHYS_BASE(reg)		(0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK(reg)		(MTRR_PHYS_BASE(reg) + 1)