cpu/amd/agesa/family15rl: Provide Richland CPU support
Richland - Microarchitecture: Piledriver Core stepping: RL-A1 CPUID: 610F31 Change-Id: I790085fbf36d836c903dcce77d794abb8578712b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7537 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan
parent
12bb8f97b6
commit
eaab6305be
|
|
@ -24,6 +24,7 @@ config CPU_AMD_AGESA
|
|||
default y if CPU_AMD_AGESA_FAMILY14
|
||||
default y if CPU_AMD_AGESA_FAMILY15
|
||||
default y if CPU_AMD_AGESA_FAMILY15_TN
|
||||
default y if CPU_AMD_AGESA_FAMILY15_RL
|
||||
default y if CPU_AMD_AGESA_FAMILY16_KB
|
||||
default n
|
||||
select ARCH_BOOTBLOCK_X86_32
|
||||
|
|
@ -83,5 +84,5 @@ source src/cpu/amd/agesa/family12/Kconfig
|
|||
source src/cpu/amd/agesa/family14/Kconfig
|
||||
source src/cpu/amd/agesa/family15/Kconfig
|
||||
source src/cpu/amd/agesa/family15tn/Kconfig
|
||||
source src/cpu/amd/agesa/family15rl/Kconfig
|
||||
source src/cpu/amd/agesa/family16kb/Kconfig
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
|
|||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
|
||||
|
||||
romstage-y += s3_resume.c
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
config CPU_AMD_AGESA_FAMILY15_RL
|
||||
bool
|
||||
select PCI_IO_CFG_EXT
|
||||
select X86_AMD_FIXED_MTRRS
|
||||
|
||||
if CPU_AMD_AGESA_FAMILY15_RL
|
||||
|
||||
config CPU_ADDR_BITS
|
||||
int
|
||||
default 48
|
||||
|
||||
config CPU_SOCKET_TYPE
|
||||
hex
|
||||
default 0x10
|
||||
|
||||
# DDR2 and REG
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0104
|
||||
|
||||
config EXT_RT_TBL_SUPPORT
|
||||
bool
|
||||
default n
|
||||
|
||||
config EXT_CONF_SUPPORT
|
||||
bool
|
||||
default n
|
||||
|
||||
config CBB
|
||||
hex
|
||||
default 0x0
|
||||
|
||||
config CDB
|
||||
hex
|
||||
default 0x18
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default 0x100000
|
||||
|
||||
config HIGH_SCRATCH_MEMORY_SIZE
|
||||
hex
|
||||
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
|
||||
default 0xA1000
|
||||
|
||||
endif # CPU_AMD_AGESA_FAMILY15_RL
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
ramstage-y += chip_name.c
|
||||
ramstage-y += model_15_init.c
|
||||
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
|
||||
|
||||
subdirs-y += ../../mtrr
|
||||
subdirs-y += ../../smm
|
||||
subdirs-y += ../../../x86/tsc
|
||||
subdirs-y += ../../../x86/lapic
|
||||
subdirs-y += ../../../x86/cache
|
||||
subdirs-y += ../../../x86/mtrr
|
||||
subdirs-y += ../../../x86/pae
|
||||
subdirs-y += ../../../x86/smm
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Processor Object
|
||||
*
|
||||
*/
|
||||
Scope (\_PR) { /* define processor scope */
|
||||
Processor(
|
||||
P000, /* name space name */
|
||||
0, /* Unique number for this processor */
|
||||
0x810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
|
||||
Processor(
|
||||
P001, /* name space name */
|
||||
1, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P002, /* name space name */
|
||||
2, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P003, /* name space name */
|
||||
3, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P004, /* name space name */
|
||||
4, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P005, /* name space name */
|
||||
5, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P006, /* name space name */
|
||||
6, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
Processor(
|
||||
P007, /* name space name */
|
||||
7, /* Unique number for this processor */
|
||||
0x0810, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
}
|
||||
} /* End _PR scope */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
* Subject to the GNU GPL v2, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
struct chip_operations cpu_amd_agesa_family15rl_ops = {
|
||||
CHIP_NAME("AMD CPU Family 15h")
|
||||
};
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/amdfam15.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <cpu/amd/agesa/s3_resume.h>
|
||||
|
||||
static void model_15_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Model 15 Init.\n");
|
||||
|
||||
u8 i;
|
||||
msr_t msr;
|
||||
int msrno;
|
||||
unsigned int cpu_idx;
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
u32 siblings;
|
||||
#endif
|
||||
|
||||
//x86_enable_cache();
|
||||
amd_setup_mtrrs();
|
||||
//x86_mtrr_check();
|
||||
disable_cache ();
|
||||
/* Enable access to AMD RdDram and WrDram extension bits */
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
|
||||
msr.lo = msr.hi = 0;
|
||||
wrmsr (0x259, msr);
|
||||
msr.lo = msr.hi = 0x1e1e1e1e;
|
||||
wrmsr(0x250, msr);
|
||||
wrmsr(0x258, msr);
|
||||
for (msrno = 0x268; msrno <= 0x26f; msrno++)
|
||||
wrmsr (msrno, msr);
|
||||
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
|
||||
wrmsr(SYSCFG_MSR, msr);
|
||||
|
||||
if (acpi_is_wakeup())
|
||||
restore_mtrr();
|
||||
|
||||
x86_mtrr_check();
|
||||
x86_enable_cache();
|
||||
|
||||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for (i = 0; i < 6; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1 << (33 - 32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
|
||||
#endif
|
||||
|
||||
/* DisableCf8ExtCfg */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi &= ~(1 << (46 - 32));
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
|
||||
cpu_idx = cpu_info()->index;
|
||||
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
|
||||
|
||||
/* Set SMM base address for this CPU */
|
||||
msr = rdmsr(MSR_SMM_BASE);
|
||||
msr.lo = SMM_BASE - (cpu_idx * 0x400);
|
||||
wrmsr(MSR_SMM_BASE, msr);
|
||||
|
||||
/* Enable the SMM memory window */
|
||||
msr = rdmsr(MSR_SMM_MASK);
|
||||
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
|
||||
wrmsr(MSR_SMM_MASK, msr);
|
||||
}
|
||||
|
||||
/* Write protect SMM space with SMMLOCK. */
|
||||
msr = rdmsr(HWCR_MSR);
|
||||
msr.lo |= (1 << 0);
|
||||
wrmsr(HWCR_MSR, msr);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_15_init,
|
||||
};
|
||||
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpu_driver model_15 __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* udelay() impementation for SMI handlers
|
||||
* This is neat in that it never writes to hardware registers, and thus does not
|
||||
* modify the state of the hardware while servicing SMIs.
|
||||
*
|
||||
* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
||||
* Subject to the GNU GPL v2, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/tsc.h>
|
||||
#include <delay.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void udelay(uint32_t us)
|
||||
{
|
||||
uint8_t fid, did, pstate_idx;
|
||||
uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
|
||||
msr_t msr;
|
||||
const uint64_t tsc_base = 100000000;
|
||||
|
||||
/* Get initial timestamp before we do the math */
|
||||
tsc_start = rdtscll();
|
||||
|
||||
/* Get the P-state. This determines which MSR to read */
|
||||
msr = rdmsr(0xc0010063);
|
||||
pstate_idx = msr.lo & 0x07;
|
||||
|
||||
/* Get FID and VID for current P-State */
|
||||
msr = rdmsr(0xc0010064 + pstate_idx);
|
||||
|
||||
/* Extract the FID and VID values */
|
||||
fid = msr.lo & 0x3f;
|
||||
did = (msr.lo >> 6) & 0x7;
|
||||
|
||||
/* Calculate the CPU clock (from base freq of 100MHz) */
|
||||
tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
|
||||
|
||||
/* Now go on and wait */
|
||||
tsc_wait_ticks = (tsc_clock / 1000000) * us;
|
||||
|
||||
do {
|
||||
tsc_now = rdtscll();
|
||||
} while (tsc_now - tsc_wait_ticks < tsc_start);
|
||||
}
|
||||
|
|
@ -28,7 +28,7 @@ void EmptyHeap(void)
|
|||
memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
|
||||
}
|
||||
|
||||
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
|
||||
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL)
|
||||
|
||||
#define AGESA_RUNTIME_SIZE 4096
|
||||
|
||||
|
|
@ -74,7 +74,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
|
|||
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
|
||||
AllocParams->BufferPointer = NULL;
|
||||
|
||||
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
|
||||
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL)
|
||||
/* if the allocation is for runtime use simple CBMEM data */
|
||||
if (Data == HEAP_CALLOUT_RUNTIME)
|
||||
return alloc_cbmem(AllocParams);
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ smm_handler_start:
|
|||
/* This is an ugly hack, and we should find a way to read the CPU index
|
||||
* without relying on the LAPIC ID.
|
||||
*/
|
||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
|
||||
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)
|
||||
/* LAPIC IDs start from 0x10; map that to the proper core index */
|
||||
subl $0x10, %ecx
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,7 +24,8 @@
|
|||
|
||||
/* On AMD's platforms we can set SMBASE by writing an MSR */
|
||||
#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \
|
||||
&& !CONFIG_CPU_AMD_AGESA_FAMILY15_TN
|
||||
&& !CONFIG_CPU_AMD_AGESA_FAMILY15_TN \
|
||||
&& !CONFIG_CPU_AMD_AGESA_FAMILY15_RL
|
||||
|
||||
// FIXME: Is this piece of code southbridge specific, or
|
||||
// can it be cleaned up so this include is not required?
|
||||
|
|
|
|||
Loading…
Reference in New Issue