vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger Lake

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Update FSP headers for Tiger Lake platform generated based on FSP
version 4133 to include post PRQ UPDs.

BUG=b:188452018
BRANCH=none
TEST=build voxel

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I493391294391c1222a1aa5fdb86baad968abf7a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54811
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

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Srinidhi N Kaushik 2021-05-21 16:16:05 -07:00 committed by Felix Held

parent 05b6b37a7c

commit eab9290b5f

2 changed files with 2138 additions and 201 deletions

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src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h

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src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h

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