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soc/intel/icelake: Use GPIO state macros from intelblocks/gpio_defs.h 

TEST=Able to build and boot ICLRVP platform.
1) Dump and disassemble DSDT to ensure GRXS function implementation
remain unchanged prior and after this CL.
2) Verify no ACPI error seen while running 'dmesg' from console.
3) abuild --timeless to ensure there are no other functional changes.

Change-Id: Iab4690341bc3da5d8eb249da4d407d84f7d4e706
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-24 13:52:39 +05:30
parent 8c0dda2183
commit eab9e86733
2 changed files with 2 additions and 3 deletions
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3
src/soc/intel/icelake/acpi/gpio.asl
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@ -1,4 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio_defs.h>
#include <soc/gpio_defs.h> #include <soc/gpio_defs.h>
#include <soc/irq.h> #include <soc/irq.h>
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
@ -114,7 +115,7 @@ Method (GRXS, 1, Serialized)
{ {
VAL0, 32 VAL0, 32
} }
Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) Local0 = (PAD_CFG0_RX_STATE & VAL0) >> PAD_CFG0_RX_STATE_BIT
Return (Local0) Return (Local0)
} }

2
src/soc/intel/icelake/include/soc/gpio_defs.h
View File

@ -257,6 +257,4 @@
#define GPI_SMI_EN_0 0x1A0 #define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600 #define PAD_CFG_BASE 0x600
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#endif #endif