src/soc/tigerlake: Add memory configuration support for Jasper Lake
BUG=none BRANCH=none TEST=Build and verify boot of WaddleDoo. Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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@ -26,6 +26,7 @@ bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c
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romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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@ -0,0 +1,119 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_
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#define _SOC_JASPERLAKE_MEMCFG_INIT_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <fsp/soc_binding.h>
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/* Number of dq bits controlled per dqs */
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#define DQ_BITS_PER_DQS 8
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/* Number of memory packages, where a "package" represents a 64-bit solution */
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#define DDR_NUM_PACKAGES 2
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/* Number of DQ byte mappings */
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#define DDR_NUM_BYTE_MAPPINGS 6
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/* 64-bit Channel identification */
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enum {
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DDR_CH0,
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DDR_CH1,
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DDR_NUM_CHANNELS
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};
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struct spd_by_pointer {
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size_t spd_data_len;
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uintptr_t spd_data_ptr;
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};
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enum mem_info_read_type {
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READ_SPD_CBFS, /* Find spd file in CBFS. */
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READ_SPD_MEMPTR /* Find spd data from pointer. */
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};
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struct spd_info {
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enum mem_info_read_type read_type;
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union spd_data_by {
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/* To identify spd file when read_type is READ_SPD_CBFS. */
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int spd_index;
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/* To find spd data when read_type is READ_SPD_MEMPTR. */
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struct spd_by_pointer spd_data_ptr_info;
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} spd_spec;
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};
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/* Board-specific memory dq mapping information */
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struct mb_cfg {
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/*
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* For each channel, there are 6 sets of DQ byte mappings,
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* where each set has a package 0 and a package 1 value (package 0
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* represents the first 64-bit lpddr4 chip combination, and package 1
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* represents the second 64-bit lpddr4 chip combination).
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* The first three sets are for CLK, CMD, and CTL.
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* The fsp package actually expects 6 sets, even though the last 3 sets
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* are not used in JSL.
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* We let the meminit_dq_dqs_map routine take care of clearing the
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* unused fields for the caller.
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* Note that dq_map is only used by LPDDR; it does not need to be
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* initialized for designs using DDR4.
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*/
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uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES];
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/*
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* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
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* mapping of a dq bit on the CPU to the bit it's connected to on
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* the memory part. The array index represents the dqs bit number
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* on the memory part, and the values in the array represent which
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* pin on the CPU that DRAM pin connects to.
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* dqs_map is only used by LPDDR; same comments apply as for dq_map
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* above.
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*/
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uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
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/*
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* Rcomp resistor values. These values represent the resistance in
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* ohms of the three rcomp resistors attached to the DDR_COMP_0,
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* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
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*/
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uint16_t rcomp_resistor[3];
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/*
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* Rcomp target values. These will typically be the following
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* values for Jasper Lake : { 80, 40, 40, 40, 30 }
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*/
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uint16_t rcomp_targets[5];
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/*
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* Early Command Training Enable/Disable Control
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* 1 = enable, 0 = disable
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*/
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uint8_t ect;
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/* Board type */
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uint8_t UserBd;
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};
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/*
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* Initialize default memory configurations for Jasper Lake.
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*/
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void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
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const struct spd_info *spd_info, bool half_populated);
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#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */
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@ -0,0 +1,120 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/meminit_jsl.h>
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#include <spd_bin.h>
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#include <string.h>
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static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
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size_t *spd_data_len)
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{
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struct region_device spd_rdev;
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size_t spd_index = spd_info->spd_spec.spd_index;
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printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
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if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
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die("spd.bin not found or incorrect index\n");
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*spd_data_len = region_device_sz(&spd_rdev);
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/* Memory leak is ok since we have memory mapped boot media */
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assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
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*spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
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}
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static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
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size_t *spd_data_len)
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{
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if (spd_info->read_type == READ_SPD_MEMPTR) {
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*spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr;
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*spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len;
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return;
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}
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if (spd_info->read_type == READ_SPD_CBFS) {
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spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len);
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return;
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}
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die("no valid way to read SPD info");
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}
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static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
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bool half_populated)
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{
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memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
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sizeof(mem_cfg->RcompResistor));
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memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
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sizeof(mem_cfg->RcompTarget));
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memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0],
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sizeof(board_cfg->dq_map[DDR_CH0]));
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memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
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sizeof(board_cfg->dqs_map[DDR_CH0]));
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if (half_populated)
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return;
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memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1],
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sizeof(board_cfg->dq_map[DDR_CH1]));
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memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
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sizeof(board_cfg->dqs_map[DDR_CH1]));
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}
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static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
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uintptr_t spd_data_ptr, bool half_populated)
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{
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/* Channel 0 */
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mem_cfg->MemorySpdPtr00 = spd_data_ptr;
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mem_cfg->MemorySpdPtr01 = 0;
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if (half_populated) {
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printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
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spd_data_ptr = 0;
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}
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/* Channel 1 */
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mem_cfg->MemorySpdPtr10 = spd_data_ptr;
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mem_cfg->MemorySpdPtr11 = 0;
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meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
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}
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/* Initialize onboard memory configurations for lpddr4x */
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void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
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const struct spd_info *spd_info, bool half_populated)
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{
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size_t spd_data_len;
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uintptr_t spd_data_ptr;
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memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
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get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
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print_spd_info((unsigned char *)spd_data_ptr);
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mem_cfg->MemorySpdDataLen = spd_data_len;
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meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
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/* Early Command Training Enabled */
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mem_cfg->ECT = board_cfg->ect;
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mem_cfg->UserBd = board_cfg->UserBd;
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}
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