src/soc/tigerlake: Add memory configuration support for Jasper Lake

BUG=none
BRANCH=none
TEST=Build and verify boot of WaddleDoo.

Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>

src/soc/intel/tigerlake/Makefile.inc

@@ -26,6 +26,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c
+romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += meminit_jsl.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c

src/soc/intel/tigerlake/include/soc/meminit_jsl.h

@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_JASPERLAKE_MEMCFG_INIT_H_
+#define _SOC_JASPERLAKE_MEMCFG_INIT_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+/* Number of dq bits controlled per dqs */
+#define DQ_BITS_PER_DQS 8
+
+/* Number of memory packages, where a "package" represents a 64-bit solution */
+#define DDR_NUM_PACKAGES 2
+
+/* Number of DQ byte mappings */
+#define DDR_NUM_BYTE_MAPPINGS 6
+
+/* 64-bit Channel identification */
+enum {
+	DDR_CH0,
+	DDR_CH1,
+	DDR_NUM_CHANNELS
+};
+
+struct spd_by_pointer {
+	size_t spd_data_len;
+	uintptr_t spd_data_ptr;
+};
+
+enum mem_info_read_type {
+	READ_SPD_CBFS,	/* Find spd file in CBFS. */
+	READ_SPD_MEMPTR	/* Find spd data from pointer. */
+};
+
+struct spd_info {
+	enum mem_info_read_type read_type;
+	union spd_data_by {
+		/* To identify spd file when read_type is READ_SPD_CBFS. */
+		int spd_index;
+
+		/* To find spd data when read_type is READ_SPD_MEMPTR. */
+		struct spd_by_pointer spd_data_ptr_info;
+	} spd_spec;
+};
+
+/* Board-specific memory dq mapping information */
+struct mb_cfg {
+
+	/*
+	 * For each channel, there are 6 sets of DQ byte mappings,
+	 * where each set has a package 0 and a package 1 value (package 0
+	 * represents the first 64-bit lpddr4 chip combination, and package 1
+	 * represents the second 64-bit lpddr4 chip combination).
+	 * The first three sets are for CLK, CMD, and CTL.
+	 * The fsp package actually expects 6 sets, even though the last 3 sets
+	 * are not used in JSL.
+	 * We let the meminit_dq_dqs_map routine take care of clearing the
+	 * unused fields for the caller.
+	 * Note that dq_map is only used by LPDDR; it does not need to be
+	 * initialized for designs using DDR4.
+	 */
+	uint8_t dq_map[DDR_NUM_CHANNELS][DDR_NUM_BYTE_MAPPINGS][DDR_NUM_PACKAGES];
+
+	/*
+	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
+	 * mapping of a dq bit on the CPU to the bit it's connected to on
+	 * the memory part.  The array index represents the dqs bit number
+	 * on the memory part, and the values in the array represent which
+	 * pin on the CPU that DRAM pin connects to.
+	 * dqs_map is only used by LPDDR; same comments apply as for dq_map
+	 * above.
+	 */
+	uint8_t dqs_map[DDR_NUM_CHANNELS][DQ_BITS_PER_DQS];
+
+	/*
+	 * Rcomp resistor values.  These values represent the resistance in
+	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
+	 * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
+	 */
+	uint16_t rcomp_resistor[3];
+
+	/*
+	 * Rcomp target values.  These will typically be the following
+	 * values for Jasper Lake : { 80, 40, 40, 40, 30 }
+	 */
+	uint16_t rcomp_targets[5];
+
+	/*
+	 * Early Command Training Enable/Disable Control
+	 * 1 = enable, 0 = disable
+	 */
+	uint8_t ect;
+
+	/* Board type */
+	uint8_t UserBd;
+};
+
+/*
+ * Initialize default memory configurations for Jasper Lake.
+ */
+
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+			const struct spd_info *spd_info, bool half_populated);
+
+#endif /* _SOC_JASPERLAKE_MEMCFG_INIT_H_ */

src/soc/intel/tigerlake/meminit_jsl.c

@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/meminit_jsl.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void spd_read_from_cbfs(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
+				size_t *spd_data_len)
+{
+	struct region_device spd_rdev;
+	size_t spd_index = spd_info->spd_spec.spd_index;
+
+	printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
+	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+		die("spd.bin not found or incorrect index\n");
+
+	*spd_data_len = region_device_sz(&spd_rdev);
+
+	/* Memory leak is ok since we have memory mapped boot media */
+	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
+
+	*spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
+}
+
+static void get_spd_data(const struct spd_info *spd_info, uintptr_t *spd_data_ptr,
+				size_t *spd_data_len)
+{
+	if (spd_info->read_type == READ_SPD_MEMPTR) {
+		*spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr;
+		*spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len;
+		return;
+	}
+
+	if (spd_info->read_type == READ_SPD_CBFS) {
+		spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len);
+		return;
+	}
+
+	die("no valid way to read SPD info");
+}
+
+static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+				bool half_populated)
+{
+	memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
+		sizeof(mem_cfg->RcompResistor));
+
+	memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
+		sizeof(mem_cfg->RcompTarget));
+
+	memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0],
+		sizeof(board_cfg->dq_map[DDR_CH0]));
+
+	memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
+		sizeof(board_cfg->dqs_map[DDR_CH0]));
+
+	if (half_populated)
+		return;
+
+	memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1],
+		sizeof(board_cfg->dq_map[DDR_CH1]));
+
+	memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
+		sizeof(board_cfg->dqs_map[DDR_CH1]));
+}
+
+static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+				uintptr_t spd_data_ptr, bool half_populated)
+{
+	/* Channel 0 */
+	mem_cfg->MemorySpdPtr00 = spd_data_ptr;
+	mem_cfg->MemorySpdPtr01 = 0;
+
+	if (half_populated) {
+		printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
+		spd_data_ptr = 0;
+	}
+
+	/* Channel 1 */
+	mem_cfg->MemorySpdPtr10 = spd_data_ptr;
+	mem_cfg->MemorySpdPtr11 = 0;
+
+	meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
+}
+
+/* Initialize onboard memory configurations for lpddr4x */
+void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
+			const struct spd_info *spd_info, bool half_populated)
+{
+	size_t spd_data_len;
+	uintptr_t spd_data_ptr;
+
+	memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
+	get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
+	print_spd_info((unsigned char *)spd_data_ptr);
+
+	mem_cfg->MemorySpdDataLen = spd_data_len;
+	meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
+
+	/* Early Command Training Enabled */
+	mem_cfg->ECT = board_cfg->ect;
+
+	mem_cfg->UserBd = board_cfg->UserBd;
+}