soc/qualcomm/sc7180: Fix set but unused variables
This fixes clang warnings. Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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@ -7,9 +7,7 @@ void mdss_intf_tg_setup(struct edid *edid)
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{
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uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x;
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uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
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uint32_t mdss_version;
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mdss_version = read32(&mdss_hw->hw_version);
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hsync_period = edid->mode.ha + edid->mode.hbl;
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vsync_period = edid->mode.va + edid->mode.vbl;
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hsync_start_x = edid->mode.hbl - edid->mode.hso;
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@ -536,8 +536,6 @@ static uint32_t dsi_phy_dsiclk_divider(struct dsi_phy_configtype *phy_cfg)
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static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg)
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{
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bool div_found = false;
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uint32_t m_val = 1;
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uint32_t n_val = 1;
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uint32_t div_ctrl = 0;
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uint32_t reg_val = 0;
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uint32_t pll_post_div = 0;
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@ -556,9 +554,6 @@ static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg
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dsi_phy_mnd_divider(phy_cfg);
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m_val = phy_cfg->pclk_divnumerator;
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n_val = phy_cfg->pclk_divdenominator;
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/* Desired clock in MHz */
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desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq;
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