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soc/qualcomm/sc7180: Fix set but unused variables 

This fixes clang warnings.

Change-Id: I407da6ec05ef646f61bd81e314fee1b5ea659192
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74557
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2023-04-19 12:39:56 +02:00 committed by Elyes Haouas
parent 830be4d3ea
commit eabae5a681
2 changed files with 0 additions and 7 deletions
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2
src/soc/qualcomm/sc7180/display/disp.c
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@ -7,9 +7,7 @@ void mdss_intf_tg_setup(struct edid *edid)
{ {
uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x; uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_version;
mdss_version = read32(&mdss_hw->hw_version);
hsync_period = edid->mode.ha + edid->mode.hbl; hsync_period = edid->mode.ha + edid->mode.hbl;
vsync_period = edid->mode.va + edid->mode.vbl; vsync_period = edid->mode.va + edid->mode.vbl;
hsync_start_x = edid->mode.hbl - edid->mode.hso; hsync_start_x = edid->mode.hbl - edid->mode.hso;

5
src/soc/qualcomm/sc7180/display/dsi_phy.c
View File

@ -536,8 +536,6 @@ static uint32_t dsi_phy_dsiclk_divider(struct dsi_phy_configtype *phy_cfg)
static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg) static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg)
{ {
bool div_found = false; bool div_found = false;
uint32_t m_val = 1;
uint32_t n_val = 1;
uint32_t div_ctrl = 0; uint32_t div_ctrl = 0;
uint32_t reg_val = 0; uint32_t reg_val = 0;
uint32_t pll_post_div = 0; uint32_t pll_post_div = 0;
@ -556,9 +554,6 @@ static unsigned long dsi_phy_calc_clk_divider(struct dsi_phy_configtype *phy_cfg
dsi_phy_mnd_divider(phy_cfg); dsi_phy_mnd_divider(phy_cfg);
m_val = phy_cfg->pclk_divnumerator;
n_val = phy_cfg->pclk_divdenominator;
/* Desired clock in MHz */ /* Desired clock in MHz */
desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq; desired_bitclk_hz = (uint64_t)phy_cfg->desired_bitclk_freq;