mb/siemens/mc_ehl1: Add GPIO configuration
Provide a valid GPIO configuration based on the mainboard wiring. Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh
Patrick Georgi
parent
8c4c572bc6
commit
eac687cc36
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@ -5,266 +5,164 @@
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/*BT_RF_KILL_N*/
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PAD_CFG_GPO(GPP_E11, 1, DEEP),
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/*WIFI_RF_KILL_N*/
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PAD_CFG_GPO(GPP_E10, 1, DEEP),
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/*M.2_WLAN_PERST_N*/
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PAD_CFG_GPO(GPD7, 1, PLTRST),
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/*M.2_WLAN_SLP*/
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PAD_CFG_GPO(GPD9, 1, PLTRST),
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/*WIFI_WAKE_N*/
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PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT),
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/*UART_BT_WAKE_N*/
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PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT),
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/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/
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PAD_CFG_GPO(GPD11, 1, PLTRST),
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/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/
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PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT),
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/*M.2_WWAN_PWR_EN*/
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PAD_CFG_GPO(GPP_F21, 1, PLTRST),
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/*M.2_WWAN_RST_N*/
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PAD_CFG_GPO(GPP_V13, 1, PLTRST),
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/*M.2_WWAN_PE_RST_N*/
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PAD_CFG_GPO(GPP_B14, 1, PLTRST),
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/*M.2_WWAN_PE_WAKE_N*/
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PAD_CFG_GPO(GPP_B17, 1, PLTRST),
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/*M.2_WWAN_FCP_OFF_N*/
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PAD_CFG_GPO(GPP_E0, 1, PLTRST),
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/*M.2_SSD_SATA_DEVSLP_1*/
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
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/*BC_PROCHOT_N*/
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PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/*FPS_RST_N*/
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PAD_CFG_GPO(GPP_V14, 1, PLTRST),
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/*FPS_INT*/
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PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE),
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/*CODEC_INT_N*/
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PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
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/*TCH_PNL_PWR_EN*/
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PAD_CFG_GPO(GPP_B16, 1, PLTRST),
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/*THC0_SPI1_INT_N*/
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PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT),
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/*SPI_TPM_INT_N*/
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PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE),
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/*EMMC_CMD*/
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PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1),
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/*EMMC_DATA0*/
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PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1),
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/*EMMC_DATA1*/
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PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1),
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/*EMMC_DATA2*/
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PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1),
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/*EMMC_DATA3*/
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PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1),
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/*EMMC_DATA4*/
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PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1),
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/*EMMC_DATA5*/
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PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1),
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/*EMMC_DATA6*/
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PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1),
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/*EMMC_DATA7*/
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PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1),
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/*EMMC_RCLK*/
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PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1),
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/*EMMC_CLK*/
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PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1),
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/*EMMC_RESET*/
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PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1),
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/*ACPRESENT*/
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PAD_CFG_NF(GPD1, NONE, PLTRST, NF1),
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/*RGMII0_MDC*/
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/*RGMII0_MDIO*/
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/*RGMII0_INT*/
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PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1),
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/*RGMII0_RESETB*/
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PAD_CFG_GPO(GPP_T5, 1, DEEP),
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/*RGMII0_AUXTS*/
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PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/*RGMII0_PPS*/
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
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/*RGMII1_MDC*/
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/*RGMII1_MDIO*/
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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/*RGMII1_INT*/
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PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
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/*RGMII1_RESETB*/
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PAD_CFG_GPO(GPP_H1, 1, DEEP),
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/*RGMII1_AUXTS*/
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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/*RGMII1_PPS*/
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
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/*RGMII2_MDC*/
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/*RGMII2_MDIO*/
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/*RGMII2_INT*/
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PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1),
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/*RGMII2_RESETB*/
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PAD_CFG_GPO(GPP_U1, 1, DEEP),
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/* Community 0 - GpioGroup GPP_B */
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PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
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PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
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PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */
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PAD_NC(GPP_B9, NONE), /* Not connected */
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PAD_NC(GPP_B10, NONE), /* Not connected */
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PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */
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PAD_NC(GPP_B14, NONE), /* Not connected */
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PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */
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PAD_NC(GPP_B18, NONE), /* Not connected */
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PAD_NC(GPP_B19, NONE), /* Not connected */
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PAD_NC(GPP_B20, NONE), /* Not connected */
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PAD_NC(GPP_B21, NONE), /* Not connected */
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PAD_NC(GPP_B22, NONE), /* Not connected */
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PAD_NC(GPP_B23, NONE), /* Not connected */
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/* Community 0 - GpioGroup GPP_T */
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PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */
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PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */
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PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
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PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
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PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
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PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
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/* Community 0 - GpioGroup GPP_G */
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PAD_NC(GPP_G8, NONE), /* Not connected */
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PAD_NC(GPP_G9, NONE), /* Not connected */
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PAD_NC(GPP_G12, NONE), /* Not connected */
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PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */
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PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */
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PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */
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PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */
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PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */
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PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */
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PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */
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PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */
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/* Community 1 - GpioGroup GPP_V */
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PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */
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PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */
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PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */
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PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */
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PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */
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PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */
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PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */
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PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */
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PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */
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PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */
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PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */
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PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */
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/* Community 1 - GpioGroup GPP_H */
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PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */
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PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */
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PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */
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PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */
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PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */
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PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */
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/* Community 1 - GpioGroup GPP_D */
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PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */
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/* Community 1 - GpioGroup GPP_U */
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PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */
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PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */
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PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */
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PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */
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PAD_NC(GPP_U12, NONE), /* Not connected */
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PAD_NC(GPP_U13, NONE), /* Not connected */
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PAD_NC(GPP_U16, NONE), /* Not connected */
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PAD_NC(GPP_U17, NONE), /* Not connected */
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PAD_NC(GPP_U18, NONE), /* Not connected */
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PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */
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/* Community 2 - GpioGroup DSW */
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PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */
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PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */
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PAD_NC(GPD7, NONE), /* Not connected */
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PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */
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/* Community 3 - GpioGroup GPP_S */
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PAD_NC(GPP_S0, NONE), /* Not connected */
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PAD_NC(GPP_S1, NONE), /* Not connected */
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/* Community 3 - GpioGroup GPP_A */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
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PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
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PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
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PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
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PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
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PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
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/* Community 4 - GpioGroup GPP_C */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
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PAD_NC(GPP_C5, NONE), /* Not connected */
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
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PAD_NC(GPP_C8, NONE), /* Not connected */
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PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */
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/* Community 4 - GpioGroup GPP_F */
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PAD_NC(GPP_F0, NONE), /* Not connected */
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PAD_NC(GPP_F1, NONE), /* Not connected */
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PAD_NC(GPP_F2, NONE), /* Not connected */
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PAD_NC(GPP_F3, NONE), /* Not connected */
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PAD_NC(GPP_F4, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F5, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F7, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F8, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F10, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F11, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F12, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F13, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F14, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F15, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F16, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F17, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F20, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F21, NONE), /* Not connected */
|
||||
|
||||
/* Community 4 - GpioGroup GPP_E */
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
|
||||
PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */
|
||||
PAD_NC(GPP_E6, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */
|
||||
PAD_NC(GPP_E15, NONE), /* Not connected */
|
||||
PAD_NC(GPP_E16, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */
|
||||
PAD_NC(GPP_E23, NONE), /* Not connected */
|
||||
|
||||
/* Community 5 - GpioGroup GPP_R */
|
||||
PAD_NC(GPP_R1, NONE), /* Not connected */
|
||||
PAD_NC(GPP_R2, NONE), /* Not connected */
|
||||
PAD_NC(GPP_R3, NONE), /* Not connected */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* UART1 RX */
|
||||
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),
|
||||
|
||||
/* UART1 TX */
|
||||
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),
|
||||
|
||||
/* UART2 RX */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4),
|
||||
|
||||
/* UART2 TX */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4),
|
||||
|
||||
/*WWAN_FCP_OFF_N*/
|
||||
PAD_CFG_GPO(GPP_E0, 1, PLTRST),
|
||||
|
||||
/*WWAN_PWREN*/
|
||||
PAD_CFG_GPO(GPP_F21, 1, PLTRST),
|
||||
|
||||
/*WWAN_PERST_N*/
|
||||
PAD_CFG_GPO(GPP_B14, 0, PLTRST),
|
||||
|
||||
/*WWAN_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V13, 0, PLTRST),
|
||||
|
||||
/* LAN_WAKEB*/
|
||||
PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT),
|
||||
|
||||
/*WWAN_RST_N*/
|
||||
PAD_CFG_GPO(GPP_V13, 0, PWROK),
|
||||
|
||||
/*WWAN_PERST_N*/
|
||||
PAD_CFG_GPO(GPP_B14, 0, PWROK),
|
||||
|
||||
/*WWAN_FCP_OFF_N*/
|
||||
PAD_CFG_GPO(GPP_E0, 0, PWROK),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
|
|
|
|||
Loading…
Reference in New Issue