src: Get rid of duplicated includes

Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/arch/x86/pirq_routing.c

@@ -18,7 +18,6 @@
 #include <arch/pirq_routing.h>
 #include <string.h>
 #include <device/pci.h>
-#include <arch/pirq_routing.h>
 
 void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
 {

src/commonlib/storage/mmc.c

@@ -21,7 +21,6 @@
 
 #include <commonlib/storage.h>
 #include <delay.h>
-#include "sd_mmc.h"
 #include "mmc.h"
 #include "sd_mmc.h"
 #include "storage.h"

src/lib/prog_loaders.c

@@ -29,7 +29,6 @@
 #include <stage_cache.h>
 #include <symbols.h>
 #include <timestamp.h>
-#include <cbfs.h>
 #include <fit_payload.h>
 
 /* Only can represent up to 1 byte less than size_t. */

src/mainboard/advansus/a785e-i/romstage.c

@@ -29,7 +29,6 @@
 #include <console/console.h>
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>

src/mainboard/amd/bimini_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/msr.h>

src/mainboard/amd/db-ft3b-lc/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/amd/lamar/mptable.c

@@ -22,7 +22,6 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
 #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
 #include <northbridge/amd/pi/00630F01/pci_devs.h>
 

src/mainboard/amd/lamar/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_defs.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <superio/fintek/f81216h/f81216h.h>

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -33,7 +33,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/amd/olivehillplus/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c

@@ -13,7 +13,6 @@
 
 #include <device/device.h>
 #include <arch/acpi.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include "mainboard.h"
 

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
 #include <spd.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/apple/macbook21/mainboard.c

@@ -21,7 +21,6 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
-#include <arch/io.h>
 #include <arch/interrupt.h>
 #include <northbridge/intel/i945/i945.h>
 #include <arch/x86/include/arch/acpigen.h>

src/mainboard/asus/kcma-d8/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <cpu/x86/bist.h>

src/mainboard/asus/kfsn4-dre/get_bus_conf.c

@@ -26,7 +26,6 @@
 #include <stdlib.h>
 #include <cpu/amd/multicore.h>
 #include <cpu/amd/amdfam10_sysconf.h>
-#include <stdlib.h>
 
 /*
  * Global variables for MB layouts and these will be shared by irqtable,

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -39,7 +39,6 @@
 #include <southbridge/amd/common/reset.h>
 #include <southbridge/nvidia/ck804/early_smbus.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include <cpu/x86/bist.h>

src/mainboard/asus/kgpe-d16/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <cpu/x86/bist.h>

src/mainboard/asus/m4a78-em/romstage.c

@@ -32,7 +32,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/asus/m4a785-m/romstage.c

@@ -33,7 +33,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/asus/m5a88-v/romstage.c

@@ -32,7 +32,6 @@
 #include <console/console.h>
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/avalue/eax-785e/romstage.c

@@ -30,7 +30,6 @@
 #include <console/console.h>
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/bap/ode_e21XX/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f81866d/f81866d.h>

src/mainboard/cavium/cn8100_sff_evb/mainboard.c

@@ -25,7 +25,6 @@
 #include <soc/uart.h>
 #include <console/console.h>
 #include <soc/clock.h>
-#include <soc/gpio.h>
 #include <soc/timer.h>
 #include <soc/cpu.h>
 #include <soc/sdram.h>

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -29,7 +29,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -29,7 +29,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -32,7 +32,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>

src/mainboard/google/jecht/smihandler.c

@@ -25,8 +25,6 @@
 #include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/nvs.h>
-#include <soc/pm.h>
-#include <soc/smm.h>
 #include "onboard.h"
 
 int mainboard_io_trap_handler(int smif)

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -39,7 +39,6 @@
 #include <lib.h>
 #include <spd.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/serverengines/pilot/pilot.h>
 #include <superio/nsc/pc87417/pc87417.h>
 #include <cpu/x86/bist.h>

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>

src/mainboard/jetway/pa78vm5/romstage.c

@@ -33,7 +33,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/fintek/common/fintek.h>

src/mainboard/lenovo/x60/dock.c

@@ -18,7 +18,6 @@
 #include <device/device.h>
 #include <arch/io.h>
 #include <delay.h>
-#include <arch/io.h>
 #include "dock.h"
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <superio/nsc/pc87392/pc87392.h>

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/opencellular/elgon/mainboard.c

@@ -24,14 +24,12 @@
 #include <soc/uart.h>
 #include <console/console.h>
 #include <soc/clock.h>
-#include <soc/gpio.h>
 #include <soc/timer.h>
 #include <soc/cpu.h>
 #include <soc/sdram.h>
 #include <soc/spi.h>
 #include <spi_flash.h>
 #include <fmap.h>
-#include <libbdk-hal/bdk-config.h>
 
 static void mainboard_print_info(void)
 {

src/mainboard/packardbell/ms2290/mainboard.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
-#include <arch/io.h>
 #include <northbridge/intel/nehalem/nehalem.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/acpi/ec.h>

src/mainboard/pcengines/apu2/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <lib.h>
-#include <cpu/x86/lapic.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/msr.h>

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -32,7 +32,6 @@
 #include <spd.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <delay.h>
-#include <cpu/x86/lapic.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/via/epia-m850/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <lib.h>
 #include <cpu/x86/bist.h>

src/northbridge/amd/amdmct/mct_ddr3/s3utils.c

@@ -30,8 +30,6 @@
 #include <spi_flash.h>
 #include <pc80/mc146818rtc.h>
 #include <inttypes.h>
-#include <console/console.h>
-#include <string.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 

src/northbridge/amd/pi/00630F01/northbridge.c

@@ -33,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <assert.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

src/northbridge/amd/pi/00660F01/northbridge.c

@@ -33,7 +33,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)

src/northbridge/amd/pi/00730F01/northbridge.c

@@ -35,7 +35,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)

src/northbridge/intel/fsp_rangeley/acpi.c

@@ -24,7 +24,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include "northbridge.h"
 

src/northbridge/intel/gm45/acpi.c

@@ -23,7 +23,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cbmem.h>
-#include <arch/acpigen.h>
 #include "gm45.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)

src/northbridge/intel/gm45/northbridge.c

@@ -25,7 +25,6 @@
 #include <cpu/cpu.h>
 #include <boot/tables.h>
 #include <arch/acpi.h>
-#include <cbmem.h>
 #include <cpu/intel/smm/gen1/smi.h>
 #include "chip.h"
 #include "gm45.h"

src/northbridge/intel/i945/acpi.c

@@ -23,7 +23,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cbmem.h>
-#include <arch/acpigen.h>
 #include "i945.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)

src/northbridge/intel/i945/northbridge.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
-#include <cbmem.h>
 #include <cpu/cpu.h>
 #include <arch/acpi.h>
 #include "i945.h"

src/northbridge/intel/i945/raminit.c

@@ -23,7 +23,6 @@
 #include <spd.h>
 #include <string.h>
 #include <halt.h>
-#include <lib.h>
 #include "raminit.h"
 #include "i945.h"
 #include "chip.h"

src/northbridge/intel/x4x/acpi.c

@@ -24,7 +24,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cbmem.h>
-#include <arch/acpigen.h>
 #include "x4x.h"
 
 unsigned long acpi_fill_mcfg(unsigned long current)

src/northbridge/via/vx900/early_vx900.h

@@ -23,7 +23,6 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <stdint.h>
-#include <arch/io.h>
 
 /* North Module devices */
 #define HOST_CTR PCI_DEV(0, 0, 0)

src/northbridge/via/vx900/raminit_ddr3.c

@@ -17,7 +17,6 @@
 #include "early_vx900.h"
 #include "raminit.h"
 #include <arch/io.h>
-#include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_ids.h>
 #include <delay.h>

src/northbridge/via/vx900/traf_ctrl.c

@@ -17,8 +17,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
 #include <drivers/generic/ioapic/chip.h>
 
 #include "vx900.h"

src/security/vboot/secdata_tpm.c

@@ -47,7 +47,6 @@
 #include <stdio.h>
 #define VBDEBUG(format, args...) printf(format, ## args)
 #else
-#include <console/console.h>
 #define VBDEBUG(format, args...) \
 	printk(BIOS_INFO, "%s():%d: " format,  __func__, __LINE__, ## args)
 #endif

src/soc/cavium/cn81xx/soc.c

@@ -32,7 +32,6 @@
 #include <soc/ecam0.h>
 #include <console/uart.h>
 #include <libbdk-hal/bdk-pcie.h>
-#include <soc/ecam0.h>
 #include <device/pci.h>
 #include <libbdk-hal/bdk-qlm.h>
 #include <libbdk-hal/bdk-config.h>

src/soc/intel/apollolake/chip.c

@@ -33,7 +33,6 @@
 #include <intelblocks/xdci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
-#include <intelblocks/acpi.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/itss.h>
 #include <intelblocks/pmclib.h>

src/soc/intel/apollolake/include/soc/pci_devs.h

@@ -23,7 +23,6 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#include <device/pci_def.h>
 #define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
 #define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #else

src/soc/intel/baytrail/acpi.c

@@ -21,7 +21,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <console/console.h>
 #include <types.h>
 #include <string.h>
 #include <cpu/x86/msr.h>

src/soc/intel/baytrail/southcluster.c

@@ -37,7 +37,6 @@
 #include <soc/ramstage.h>
 #include <soc/spi.h>
 #include "chip.h"
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 
 static inline void

src/soc/intel/braswell/romstage/romstage.c

@@ -21,7 +21,6 @@
 #include <arch/io.h>
 #include <arch/cbfs.h>
 #include <arch/stages.h>
-#include <cbmem.h>
 #include <chip.h>
 #include <cpu/x86/mtrr.h>
 #include <console/console.h>

src/soc/intel/broadwell/lpc.c

@@ -42,9 +42,7 @@
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
 #include <soc/intel/broadwell/chip.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
-#include <cpu/cpu.h>
 
 static void pch_enable_ioapic(struct device *dev)
 {

src/soc/intel/broadwell/refcode.c

@@ -22,7 +22,6 @@
 #include <program_loading.h>
 #include <rmodule.h>
 #include <stage_cache.h>
-#include <string.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>

src/soc/intel/cannonlake/include/soc/pci_devs.h

@@ -25,7 +25,6 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#include <device/pci_def.h>
 #define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
 #define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #else

src/soc/intel/denverton_ns/systemagent.c

@@ -27,7 +27,6 @@
 #include <string.h>
 #include <cbmem.h>
 #include <romstage_handoff.h>
-#include <delay.h>
 #include <timer.h>
 
 #include <soc/iomap.h>

src/soc/intel/fsp_baytrail/acpi.c

@@ -35,14 +35,12 @@
 #include <string.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
-#include <soc/pci_devs.h>
 #include <soc/pmc.h>
 #include <soc/irq.h>
 #include <soc/iosf.h>
 #include <arch/io.h>
 #include <soc/msr.h>
 #include <soc/pattrs.h>
-#include <soc/pmc.h>
 #include <cbmem.h>
 
 #include "chip.h"

src/soc/intel/fsp_baytrail/northcluster.c

@@ -24,7 +24,6 @@
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
-#include <device/pci.h>
 #include <cbmem.h>
 #include <soc/baytrail.h>
 #include <drivers/intel/fsp1_0/fsp_util.h>

src/soc/intel/icelake/include/soc/pci_devs.h

@@ -24,7 +24,6 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#include <device/pci_def.h>
 #define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
 #define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #else

src/soc/intel/skylake/chip_fsp20.c

@@ -20,13 +20,9 @@
 #include <fsp/api.h>
 #include <arch/acpi.h>
 #include <arch/io.h>
-#include <chip.h>
-#include <bootstate.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <device/pci.h>
 #include <device/pci_ids.h>
-#include <fsp/api.h>
 #include <fsp/util.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/itss.h>

src/soc/intel/skylake/elog.c

@@ -24,7 +24,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/smbus.h>
-#include <stdint.h>
 
 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {

src/soc/intel/skylake/include/soc/pci_devs.h

@@ -25,7 +25,6 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#include <device/pci_def.h>
 #define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
 #define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #else

src/soc/nvidia/tegra124/display.c

@@ -29,7 +29,6 @@
 #include <soc/nvidia/tegra/pwm.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <stdlib.h>
 #include <string.h>
 
 #include "chip.h"

src/soc/nvidia/tegra210/sor.c

@@ -24,7 +24,6 @@
 #include <delay.h>
 #include <soc/addressmap.h>
 #include <device/device.h>
-#include <stdlib.h>
 #include <string.h>
 #include <boot/tables.h>
 #include <cbmem.h>

src/southbridge/amd/cimx/sb900/SbPlatform.h

@@ -56,7 +56,6 @@ typedef union _PCI_ADDR {
 #include "SbType.h"
 #include "AcpiLib.h"
 #include "SbDef.h"
-#include "AmdSbLib.h"
 #include "SbSubFun.h"
 #include "platform_cfg.h"	/* mainboard specific configuration */
 #include <OEM.h>		/* platform default configuration */

src/southbridge/intel/bd82x6x/lpc.c

@@ -32,7 +32,6 @@
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
-#include <cpu/x86/smm.h>
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>

src/southbridge/intel/bd82x6x/me.c

@@ -32,11 +32,9 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"

src/southbridge/intel/bd82x6x/me_8.x.c

@@ -32,11 +32,9 @@
 #include <elog.h>
 #include <halt.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"

src/southbridge/intel/bd82x6x/smihandler.c

@@ -28,7 +28,6 @@
 #include "nvs.h"
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <arch/io.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/intel/model_206ax/model_206ax.h>

src/southbridge/intel/common/spi.c

@@ -37,7 +37,6 @@
 
 
 #ifdef __SMM__
-#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\
@@ -52,7 +51,6 @@
 	pci_write_config32(dev, reg, val)
 #else /* !__SMM__ */
 #include <device/device.h>
-#include <device/pci.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\

src/southbridge/intel/fsp_rangeley/early_init.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <pc80/mc146818rtc.h>
 #include <version.h>
-#include <device/pci_def.h>
 #include "pci_devs.h"
 #include "soc.h"
 

src/southbridge/intel/fsp_rangeley/lpc.c

@@ -29,7 +29,6 @@
 #include <elog.h>
 #include <string.h>
 #include <cbmem.h>
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include "soc.h"
 #include "irq.h"

src/southbridge/intel/fsp_rangeley/soc.h

@@ -62,7 +62,6 @@ int soc_silicon_type(void);
 int soc_silicon_supported(int type, int rev);
 void soc_enable(struct device *dev);
 
-#include <arch/acpi.h>
 void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
 
 #if IS_ENABLED(CONFIG_ELOG)

src/southbridge/intel/fsp_rangeley/spi.c

@@ -29,7 +29,6 @@
 static int ich_status_poll(u16 bitmask, int wait_til_set);
 
 #ifdef __SMM__
-#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\

src/southbridge/intel/ibexpeak/me.c

@@ -31,11 +31,9 @@
 #include <delay.h>
 #include <elog.h>
 
-#ifdef __SMM__
-#include <arch/io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
+#ifndef __SMM__
+#include <device/device.h>
+#include <device/pci.h>
 #endif
 
 #include "me.h"

src/southbridge/intel/ibexpeak/smihandler.c

@@ -34,7 +34,6 @@
  */
 #include <northbridge/intel/nehalem/nehalem.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/io.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value

src/southbridge/intel/lynxpoint/lpc.c

@@ -33,7 +33,6 @@
 #include "nvs.h"
 #include "pch.h"
 #include <arch/acpigen.h>
-#include <cbmem.h>
 #include <drivers/intel/gma/i915.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
 #include <southbridge/intel/common/rtc.h>

src/southbridge/intel/lynxpoint/pch.h

@@ -174,7 +174,6 @@ void disable_gpe(u32 mask);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
-#include <arch/acpi.h>
 #include "chip.h"
 void pch_enable(struct device *dev);
 void pch_disable_devfn(struct device *dev);

src/southbridge/nvidia/mcp55/lpc.c

@@ -33,7 +33,6 @@
 #include <arch/acpi.h>
 #include <stdlib.h>
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #endif
 #include <cpu/amd/powernow.h>