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cpu/x86: Define MTRR_CAP_PRMRR 

Followups will remove remaining cases of PRMRR_SUPPORTED and
SMRR_SUPPORTED in the tree.

Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-06-11 09:52:45 +03:00 committed by Patrick Georgi
parent 96cb2522fd
commit eadd251bf7
5 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/x86/mtrr/debug.c
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@ -92,8 +92,9 @@ static void display_mtrrcap(void)
msr = rdmsr(MTRR_CAP_MSR); msr = rdmsr(MTRR_CAP_MSR);
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n", "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n",
msr.hi, msr.lo, msr.hi, msr.lo,
(msr.lo & MTRR_CAP_PRMRR) ? "PRMRR, " : "",
(msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "",
(msr.lo & MTRR_CAP_WC) ? "WC, " : "", (msr.lo & MTRR_CAP_WC) ? "WC, " : "",
(msr.lo & MTRR_CAP_FIX) ? "FIX, " : "", (msr.lo & MTRR_CAP_FIX) ? "FIX, " : "",

1
src/include/cpu/x86/mtrr.h
View File

@ -16,6 +16,7 @@
#define MTRR_CAP_MSR 0x0fe #define MTRR_CAP_MSR 0x0fe
#define MTRR_CAP_PRMRR (1 << 12)
#define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_SMRR (1 << 11)
#define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_WC (1 << 10)
#define MTRR_CAP_FIX (1 << 8) #define MTRR_CAP_FIX (1 << 8)

2
src/soc/intel/cannonlake/cpu.c
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@ -312,6 +312,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
if (msr2.lo && (current_patch_id == new_patch_id - 1)) if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0; return 0;
return (msr1.lo & PRMRR_SUPPORTED) && return (msr1.lo & MTRR_CAP_PRMRR) &&
(current_patch_id == new_patch_id - 1); (current_patch_id == new_patch_id - 1);
} }

2
src/soc/intel/common/block/sgx/sgx.c
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@ -28,7 +28,7 @@ static int is_sgx_supported(void)
cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */ cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */
msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */
return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED)); return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR));
} }
void prmrr_core_configure(void) void prmrr_core_configure(void)

2
src/soc/intel/skylake/cpu.c
View File

@ -355,6 +355,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
if (msr2.lo && (current_patch_id == new_patch_id - 1)) if (msr2.lo && (current_patch_id == new_patch_id - 1))
return 0; return 0;
else else
return (msr1.lo & PRMRR_SUPPORTED) && return (msr1.lo & MTRR_CAP_PRMRR) &&
(current_patch_id == new_patch_id - 1); (current_patch_id == new_patch_id - 1);
} }