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mb/google/hatch: Add noise mitigation setting for dratini/jinlon 

Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8
and disable Fast PKG C State Ramp (IA, GT, SA).

BRANCH=hatch
BUG=b:143501884
TEST=build and verify that noise reduce.

Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wisley Chen 2020-01-06 17:44:10 +08:00 committed by Shelley Chen
parent a547584445
commit eae254efb3
2 changed files with 18 additions and 0 deletions
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9
src/mainboard/google/hatch/variants/dratini/overridetree.cb
View File

@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled,
}" }"
# VR Slew rate setting
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2"
register "FastPkgCRampDisableIa" = "1"
register "FastPkgCRampDisableGt" = "1"
register "FastPkgCRampDisableSa" = "1"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |

9
src/mainboard/google/hatch/variants/jinlon/overridetree.cb
View File

@ -17,6 +17,15 @@ chip soc/intel/cannonlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled,
}" }"
# VR Slew rate setting
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2"
register "FastPkgCRampDisableIa" = "1"
register "FastPkgCRampDisableGt" = "1"
register "FastPkgCRampDisableSa" = "1"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |