sb/amd/pi/hudson: drop HUDSON_UART option and corresponding code

This option is neither selected nor usable for the only remaining SoC
that uses this code, so drop the remaining parts. configure_hudson_uart
isn't called anywhere and isn't even compiled, since it's guarded by an
#if CONFIG(HUDSON_UART) block and the HUDSON_UART Kconfig option isn't
selected anywhere. Both the offsets used in the iomux_write8 calls and
the UART controller itself aren't listed in the BKDG #52740 Rev 3.05 for
the AMD Family 16h Models 30h-3Fh APUs which is the only SoC that uses
this code, so the code didn't even apply for this chip.

TEST=Timeless build for pcengines/apu2 results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/southbridge/amd/pi/hudson/Kconfig

@@ -205,18 +205,3 @@ config HUDSON_ACPI_IO_BASE
 	  This value must match the hardcoded value of AGESA.
 
 endif
-
-config HUDSON_UART
-	bool "UART controller on Kern"
-	default n
-	depends on SOUTHBRIDGE_AMD_PI_KERN
-	select DRIVERS_UART_8250MEM
-	select DRIVERS_UART_8250MEM_32
-	select NO_UART_ON_SUPERIO
-	select UART_OVERRIDE_REFCLK
-	help
-	  There are two UART controllers in Kern.
-	  The UART registers are memory-mapped. UART
-	  controller 0 registers range from FEDC_6000h
-	  to FEDC_6FFFh. UART controller 1 registers
-	  range from FEDC_8000h to FEDC_8FFFh.

src/southbridge/amd/pi/hudson/Makefile.inc

@@ -33,10 +33,8 @@ romstage-y += enable_usbdebug.c
 romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
-romstage-$(CONFIG_HUDSON_UART) += uart.c
 
 verstage-y += early_setup.c
-verstage-$(CONFIG_HUDSON_UART) += uart.c
 
 ramstage-y += enable_usbdebug.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
@@ -52,7 +50,6 @@ ramstage-y += sd.c
 ramstage-y += sm.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
-ramstage-$(CONFIG_HUDSON_UART) += uart.c
 ramstage-y += usb.c
 
 all-y += reset.c

src/southbridge/amd/pi/hudson/early_setup.c

@@ -13,33 +13,6 @@
 #include "pci_devs.h"
 #include <Fch/Fch.h>
 
-#if CONFIG(HUDSON_UART)
-
-#include <delay.h>
-
-void configure_hudson_uart(void)
-{
-	u8 byte;
-
-	byte = aoac_read8(FCH_AOAC_REG56 +
-			  CONFIG_UART_FOR_CONSOLE * sizeof(u16)));
-	byte |= 1 << 3;
-	aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)),
-		    byte);
-
-	aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3));
-	iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */
-	iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */
-	iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */
-	iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */
-
-	udelay(2000);
-	write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88),
-			0x01); /* reset UART */
-}
-
-#endif
-
 void hudson_pci_port80(void)
 {
 	u8 byte;

src/southbridge/amd/pi/hudson/hudson.h

@@ -170,7 +170,6 @@ void hudson_set_readspeed(u16 norm, u16 fast);
 void lpc_wideio_512_window(uint16_t base);
 void lpc_wideio_16_window(uint16_t base);
 void hudson_tpm_decode_spi(void);
-void configure_hudson_uart(void);
 
 void hudson_enable(struct device *dev);
 void s3_resume_init_data(void *FchParams);

src/southbridge/amd/pi/hudson/uart.c

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/uart.h>
-
-uintptr_t uart_platform_base(unsigned int idx)
-{
-	return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1));
-}
-
-unsigned int uart_platform_refclk(void)
-{
-	return 48000000;
-}