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mb/google/hatch: Configure I2C buses 

This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.

BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.

Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2019-02-04 23:03:04 -08:00
parent 946fa5f941
commit eaf83489f6
2 changed files with 20 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -214,8 +214,8 @@ chip soc/intel/cannonlake
device i2c 49 on end
end
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
@ -223,7 +223,7 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA
device pci 19.0 off end # I2C #4
device pci 19.0 on end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC

17
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -144,6 +144,23 @@ static const struct pad_config gpio_table[] = {
/* SD_WP => NC */
PAD_NC(GPP_G7, DN_20K),
/* PCH_I2C_PEN_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* PCH_I2C_PEN_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* PCH_I2C_SAR0_MST_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* PCH_I2C_SAR0_MST_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* PCH_I2C_M2_AUDIO_SAR1_SDA */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
/* PCH_I2C_M2_AUDIO_SAR1_SCL */
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
/* PCH_I2C_TRACKPAD_SDA */
PAD_NC(GPP_H10, NONE),
/* PCH_I2C_TRACKPAD_SCL */
PAD_NC(GPP_H11, NONE),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
};