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- Commit a working pirq table for the AMD solo 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2003-04-25 02:02:25 +00:00
parent 825dd3361b
commit eb00fa5c11
3 changed files with 17 additions and 16 deletions
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3
src/arch/i386/boot/pirq_routing.c
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@ -28,7 +28,8 @@ void check_pirq_routing_table(void)
printk_debug("%s:%6d:%s() - irq_routing_table located at: 0x%p\n", printk_debug("%s:%6d:%s() - irq_routing_table located at: 0x%p\n",
__FILE__, __LINE__, __FUNCTION__, addr); __FILE__, __LINE__, __FUNCTION__, addr);
sum = (unsigned char)(rt->checksum-sum);
sum = rt->checksum - sum;
if (sum != rt->checksum) { if (sum != rt->checksum) {
printk_warning("%s:%6d:%s() - " printk_warning("%s:%6d:%s() - "

22
src/mainboard/amd/solo/irq_tables.c
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@ -12,20 +12,20 @@ const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*7, /* there can be total 7 devices on the bus */ 32+16*7, /* there can be total 7 devices on the bus */
0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (bus) */
0x38, /* Where the interrupt router lies (dev) */ (5<<3)|3, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */ 0xc20, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */ 0x1022, /* Vendor */
0x7468, /* Device */ 0x746b, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x39, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0xdf, /* u8 checksum , mod 256 checksum must give zero */
{ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x2,0x28, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, {0x02, (5<<3)|0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x02, 0x00},
{0x2,0x30, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0x3, 0}, {0x02, (6<<3)|0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x03, 0x00},
{0x2,0x38, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x4, 0}, {0x02, (7<<3)|0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x04, 0x00},
{0x2,0x8, {{0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}}, 0, 0}, {0x02, (1<<3)|1, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}}, 0x00, 0x00},
{0,0x39, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, {0x00, (5<<3)|1, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, {0x00, (2<<3)|0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
{0xff,0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff}, {0xff, 0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff},
} }
}; };

2
src/northbridge/amd/amdk8/northbridge.c
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@ -13,7 +13,7 @@ struct mem_range *sizeram(void)
mem[0].basek = 0; mem[0].basek = 0;
mem[0].sizek = 640; mem[0].sizek = 640;
mem[1].basek = 1024; mem[1].basek = 960;
mem[1].sizek = size - mem[1].basek; mem[1].sizek = size - mem[1].basek;
mem[2].basek = 0; mem[2].basek = 0;
mem[2].sizek = 0; mem[2].sizek = 0;