mb/google/hatch: Initialize all gpios
BUG=b:123490912 BRANCH=None TEST=flash BIOS and make sure hatch boots up properly Change-Id: I9e41f0b38703f2c7a2b5a7ac9b108f8f10070004 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31724 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen
parent
91b027a351
commit
eb2fa5cd39
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@ -19,182 +19,387 @@
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* SD_1P8_SEL => NC */
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PAD_NC(GPP_A16, DN_20K),
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/* EN_PP3300_SD_DX */
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/* A0 : SAR0_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A0, NONE, DEEP, LEVEL, NONE),
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/* A1 : ESPI_IO0 */
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/* A2 : ESPI_IO1 */
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/* A3 : ESPI_IO2 */
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/* A4 : ESPI_IO3 */
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/* A5 : ESPI_CS# */
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/* A6 : SAR1_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE),
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/* A7 : PP3300_SOC_A */
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PAD_NC(GPP_A7, NONE),
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/* A8 : EMR_GARAGE_DET ==> NC */
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PAD_NC(GPP_A8, NONE),
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/* A9 : ESPI_CLK */
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/* A10 : PEN_RESET_ODL */
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PAD_NC(GPP_A10, NONE),
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/* A11 : PCH_SPI_FPMCU_CS_L */
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PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
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/* A12 : FPMCU_RST_ODL */
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PAD_CFG_GPO(GPP_A12, 1, DEEP),
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/* A13 : SUSWARN_L */
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* A14 : ESPI_RST_L */
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/* A15 : SUSACK_L */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* A16 : SD_1P8_SEL => NC */
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PAD_NC(GPP_A16, NONE),
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/* A17 : EN_PP3300_SD_DX */
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PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* EN_PP3300_WWAN */
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/* A18 : EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_A18, 1, DEEP),
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/* WWAN_RADIO_DISABLE_1V8_ODL */
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/* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
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PAD_CFG_GPO(GPP_A19, 1, DEEP),
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/* A20 : M2_INT_L */
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PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP, LEVEL, NONE),
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/*
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* TRACKPAD_INT_ODL (wake)
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* A21 : TRACKPAD_INT_ODL (wake)
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* TODO Combine into single gpio, when ITSS IPCx configuration
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* is fixed in FSP.
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*/
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PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT),
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/* SRCCLKREQ1 */
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/* A22 : FPMCU_PCH_BOOT0 */
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PAD_CFG_GPO(GPP_A22, 0, DEEP),
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/* A23 : FPMCU_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, NONE),
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/* B0 : CORE_VID0 */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* B1 : CORE_VID1 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* B2 : GPP_B2 ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : GPP_B3 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B4 : GPP_B4 ==> NC */
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PAD_NC(GPP_B4, NONE),
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/* B5 : GPP_B5 ==> NC */
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PAD_NC(GPP_B5, NONE),
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/* B6 : SRCCLKREQ1 */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* PCIE_14_WLAN_CLKREQ_ODL */
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/* B7 : GPP_B7 ==> NC */
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PAD_NC(GPP_B7, NONE),
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/* B8 : PCIE_14_WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_CS_L */
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/* B9 : GPP_B9 ==> NC */
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PAD_NC(GPP_B9, NONE),
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/* B10 : GPP_B10 ==> NC */
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PAD_NC(GPP_B10, NONE),
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/* B11 : EXT_PWR_GATE_L */
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* B12 : SLP_S0_L */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* B13 : PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_CLK */
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MISO_R */
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* H1_SLAVE_SPI_MOSI_R */
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* GPP_C0 => NC */
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/* B19 : GPP_B19 ==> NC */
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PAD_NC(GPP_B19, NONE),
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/* B20 : PCH_SPI_FPMCU_CLK_R */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* B21 : PCH_SPI_FPMCU_MISO */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* B22 : PCH_SPI_FPMCU_MOSI */
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PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
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/* B23 : GPP_B23_STRAP */
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PAD_NC(GPP_B23, NONE),
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/* C0 : GPP_C0 => NC */
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PAD_NC(GPP_C0, NONE),
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/* PCIE_14_WLAN_WAKE_ODL */
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/* C1 : PCIE_14_WLAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
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/* GPP_C2 => NC */
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/* C2 : GPP_C2 => NC */
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PAD_NC(GPP_C2, NONE),
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/* WLAN_OFF_L */
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/* C3 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C3, 1, DEEP),
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/* TOUCHSCREEN_DIS_L */
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/* C4 : TOUCHSCREEN_DIS_L */
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PAD_CFG_GPO(GPP_C4, 1, DEEP),
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/* GPP_C5 => NC */
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/* C5 : GPP_C5 => NC */
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PAD_NC(GPP_C5, NONE),
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/* PEN_PDCT_OD_L */
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PAD_CFG_GPI(GPP_C6, NONE, DEEP),
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/* PEN_IRQ_OD_L */
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PAD_CFG_GPI_APIC(GPP_C7, NONE, DEEP, LEVEL, NONE),
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/* GPP_C10_TP */
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/* C6 : PEN_PDCT_OD_L */
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PAD_NC(GPP_C6, NONE),
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/* C7 : PEN_IRQ_OD_L */
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PAD_NC(GPP_C7, NONE),
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/* C8 : UART_PCH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* C9 : UART_PCH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* C10 : GPP_10 ==> GPP_C10_TP */
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PAD_NC(GPP_C10, DN_20K),
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/* GPP_C11_TP */
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/* C11 : GPP_11 ==> GPP_C11_TP */
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PAD_NC(GPP_C11, DN_20K),
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/* BT_DISABLE_L */
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/* C12 : GPP_C12 ==> NC */
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PAD_NC(GPP_C12, NONE),
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/* C13 : EC_PCH_INT_L
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* TODO Configure it back to invert mode, when
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* ITSS IPCx configuration is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_C13, NONE, DEEP, LEVEL, NONE),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 1, DEEP),
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/* WWAN_DPR_SAR_ODL
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/* C15 : WWAN_DPR_SAR_ODL
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*
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* TODO: Driver doesn't use this pin as of now. In case driver starts
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* using this pin, expose this pin to driver.
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*/
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* PCH_I2C_TRACKPAD_SDA */
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/* C16 : PCH_I2C_TRACKPAD_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* PCH_I2C_TRACKPAD_SCL */
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/* C17 : PCH_I2C_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* PCH_I2C_TOUCHSCREEN_SDA */
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/* C18 : PCH_I2C_TOUCHSCREEN_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* PCH_I2C_TOUCHSCREEN_SCL */
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/* C19 : PCH_I2C_TOUCHSCREEN_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* PCH_WP_OD */
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/* C20 : PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/*
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* H1_PCH_INT_ODL
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* C21 : H1_PCH_INT_ODL
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* TODO Configure it back to invert mode, when
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* ITSS IPCx configuration is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE),
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/* EC_IN_RW_OD */
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/* C22 : EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_C22, NONE, DEEP),
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/* WLAN_PE_RST# */
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* WWAN_CONFIG_0 */
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/* D0 : TP31 */
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PAD_NC(GPP_D0, NONE),
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/* D1 : TP16 */
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PAD_NC(GPP_D1, NONE),
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/* D2 : TP26 */
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PAD_NC(GPP_D2, NONE),
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/* D3 : TP27 */
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PAD_NC(GPP_D3, NONE),
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/* D4 : TP40 */
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PAD_NC(GPP_D4, NONE),
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/* D5 : WWAN_CONFIG_0 */
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PAD_NC(GPP_D5, NONE),
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/* WWAN_CONFIG_1 */
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/* D6 : WWAN_CONFIG_1 */
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PAD_NC(GPP_D6, NONE),
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/* WWAN_CONFIG_2 */
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/* D7 : WWAN_CONFIG_2 */
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PAD_NC(GPP_D7, NONE),
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/* WWAN_CONFIG_3 */
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/* D8 : WWAN_CONFIG_3 */
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PAD_NC(GPP_D8, NONE),
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/* TOUCHSCREEN_RST_L */
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/* D9 : GPP_D9 ==> NC */
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PAD_NC(GPP_D9, NONE),
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/* D10 : GPP_D10 ==> NC */
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PAD_NC(GPP_D10, NONE),
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/* D11 : GPP_D11 ==> NC */
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PAD_NC(GPP_D11, NONE),
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/* D12 : GPP_D12 */
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PAD_NC(GPP_D12, NONE),
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/* D13 : ISH_UART_RX */
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PAD_NC(GPP_D13, NONE),
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/* D14 : ISH_UART_TX */
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PAD_NC(GPP_D14, NONE),
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/* D15 : TOUCHSCREEN_RST_L */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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/*
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* TOUCHSCREEN_INT_L
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* TODO Configure it back to invert mode, when
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* ITSS IPCx configuration is fixed in FSP.
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*/
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/* D16 : USI_INT */
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PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE),
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/* D17 : PCH_HP_SDW_CLK */
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PAD_NC(GPP_D17, NONE),
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/* D18 : PCH_HP_SDW_DAT */
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PAD_NC(GPP_D18, NONE),
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/* D19 : DMIC_CLK_0_SNDW4_CLK */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* D20 : DMIC_DATA_0_SNDW4_DATA */
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PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
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/*
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* TRACKPAD_INT_ODL
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* D21 : TRACKPAD_INT_ODL
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* TODO Combine into single gpio with invert mode, when ITSS
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* IPCx configuration is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE),
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/* SATAGP1 */
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/* D22 : GPP_D22 ==> NC */
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PAD_NC(GPP_D22, NONE),
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/* D23 : SPP_MCLK */
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PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* E0 : GPP_E0 ==> NC */
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PAD_NC(GPP_E0, NONE),
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/* E1 : SATAGP1 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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/* M2_SSD_PE_WAKE_ODL */
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/* E2 : GPP_E2 ==> NC */
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PAD_NC(GPP_E2, NONE),
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/* E3 : GPP_E3 ==> NC */
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PAD_NC(GPP_E3, NONE),
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/* E4 : M2_SSD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E4, NONE, DEEP),
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/* SATA_DEVSLP1 */
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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/* USB_C_OC_OD USB_OC2*/
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/* E6 : M2_SSD_RST_L */
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PAD_NC(GPP_E6, NONE),
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/* E7 : GPP_E7 ==> NC */
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PAD_NC(GPP_E7, NONE),
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/* E8 : GPP_E8 ==> NC */
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PAD_NC(GPP_E8, NONE),
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/* E9 : GPP_E9 ==> NC */
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PAD_NC(GPP_E9, NONE),
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/* E10 : GPP_E10 ==> NC */
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PAD_NC(GPP_E10, NONE),
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/* E11 : USB_C_OC_OD USB_OC2 */
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB_A_OC_OD USB_OC3*/
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/* E12 : USB_A_OC_OD USB_OC3 */
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
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/* USB_C0_DP_HPD */
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/* E13 : USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD_ODL */
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/* E14 : DDI2_HPD_ODL */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* DDPD_HPD2 => NC */
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PAD_NC(GPP_E15, DN_20K),
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/* DDPE_HPD2 => NC */
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PAD_NC(GPP_E16, DN_20K),
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/* EDP_HPD */
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/* E15 : DDPD_HPD2 => NC */
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PAD_NC(GPP_E15, NONE),
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/* E16 : DDPE_HPD2 => NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : EDP_HPD */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK => NC */
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PAD_NC(GPP_E18, DN_20K),
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/* DDPC_CTRLCLK => NC */
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PAD_NC(GPP_E20, DN_20K),
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/* DDPD_CTRLCLK => NC */
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PAD_NC(GPP_E22, DN_20K),
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/* GPIO_WWAN_WLAN_COEX3 */
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/* E18 : DDPB_CTRLCLK => NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : GPP_E19_STRAP */
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PAD_CFG_GPI(GPP_E19, NONE, DEEP),
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/* E20 : DDPC_CTRLCLK => NC */
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PAD_NC(GPP_E20, NONE),
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/* E21 : GPP_E21_STRAP */
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PAD_CFG_GPI(GPP_E21, NONE, DEEP),
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/* E22 : DDPD_CTRLCLK => NC */
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PAD_NC(GPP_E22, NONE),
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/* E23 : GPP_E23_STRAP */
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PAD_NC(GPP_E23, NONE),
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/* F0 : GPIO_WWAN_WLAN_COEX3 */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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/* WWAN_RESET_1V8_ODL */
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/* F1 : WWAN_RESET_1V8_ODL */
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PAD_CFG_GPO(GPP_F1, 1, DEEP),
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/* UART_WWANTX_WLANRX_COEX1 */
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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/* F3 : GPP_F3 ==> NC */
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PAD_NC(GPP_F3, NONE),
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/* F4 : CNV_BRI_DT */
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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/* F5 : CNV_BRI_RSP */
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
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/* F6 : CNV_RGI_DT */
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* F7 : CNV_RGI_RSP */
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PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
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/* F8 : UART_WWANTX_WLANRX_COEX1 */
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PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
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/* UART_WWANRX_WLANTX_COEX2 */
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/* F9 : UART_WWANRX_WLANTX_COEX2 */
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PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
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||||
/* PCH_MEM_STRAP0 */
|
||||
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
|
||||
/* PCH_MEM_STRAP1 */
|
||||
PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
|
||||
/* PCH_MEM_STRAP2 */
|
||||
/* F10 : GPP_F10 ==> NC */
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
/* F11 : PCH_MEM_STRAP2 */
|
||||
PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
|
||||
/* PCH_MEM_STRAP3 */
|
||||
/* F12 : GPP_F12 ==> NC */
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
/* F13 : GPP_F13 ==> NC */
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
/* F14 : GPP_F14 ==> NC */
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
/* F15 : GPP_F15 ==> NC */
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
/* F16 : GPP_F16 ==> NC */
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
/* F17 : GPP_F17 ==> NC */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
/* F18 : GPP_F18 ==> NC */
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
/* F19 : GPP_F19 ==> NC */
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
/* F20 : PCH_MEM_STRAP0 */
|
||||
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
|
||||
/* F21 : PCH_MEM_STRAP1 */
|
||||
PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
|
||||
/* F22 : PCH_MEM_STRAP3 */
|
||||
PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
|
||||
/* SD_CMD */
|
||||
/* F23 : GPP_F23 ==> NC */
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
/* G0 : SD_CMD */
|
||||
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* SD_DATA0 */
|
||||
/* G1 : SD_DATA0 */
|
||||
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_DATA1 */
|
||||
/* G2 : SD_DATA1 */
|
||||
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_DATA2 */
|
||||
/* G3 : SD_DATA2 */
|
||||
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_DATA3 */
|
||||
/* G4 : SD_DATA3 */
|
||||
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_CD# */
|
||||
/* G5 : SD_CD# */
|
||||
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* SD_CLK */
|
||||
/* G6 : SD_CLK */
|
||||
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/* SD_WP => NC */
|
||||
/* G7 : SD_WP => NC */
|
||||
PAD_NC(GPP_G7, DN_20K),
|
||||
|
||||
/* PCH_I2C_PEN_SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_PEN_SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_SAR0_MST_SDA */
|
||||
/*
|
||||
* H0 : AUDIO IRQ
|
||||
* TODO Configure it back to invert mode, when
|
||||
* ITSS IPCx configuration is fixed in FSP.
|
||||
*/
|
||||
PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, NONE),
|
||||
/* H1 : CNV_RF_RESET_L */
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
|
||||
/* H2 : CNV_CLKREQ0 */
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
|
||||
/* H3 : SPEAKER SD MODE ENABLE */
|
||||
PAD_CFG_GPO(GPP_H3, 0, DEEP),
|
||||
/* H4 : PCH_I2C_PEN_SDA */
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
/* H5 : PCH_I2C_PEN_SCL */
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
/* H6 : PCH_I2C_SAR0_MST_SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_SAR0_MST_SCL */
|
||||
/* H7 : PCH_I2C_SAR0_MST_SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_M2_AUDIO_SAR1_SDA */
|
||||
/* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_M2_AUDIO_SAR1_SCL */
|
||||
/* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
|
||||
/* PCH_I2C_TRACKPAD_SDA */
|
||||
/* H10 : PCH_I2C_TRACKPAD_SDA */
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
/* PCH_I2C_TRACKPAD_SCL */
|
||||
/* H11 : PCH_I2C_TRACKPAD_SCL */
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
/* SD card detect VGPIO */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
|
||||
/* H12 : GPP_H12 ==> NC */
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
/* H13 : GPP_H13 ==> NC */
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
/* H14 : GPP_H14 ==> NC */
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
/* H15 : GPP_H15 ==> NC */
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
/* H16 : GPP_H16 ==> NC */
|
||||
PAD_NC(GPP_H16, NONE),
|
||||
/* H17 : TP1 */
|
||||
PAD_NC(GPP_H17, NONE),
|
||||
/* H18 : CPU_C10_GATE_L */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
/* H19 : GPP_H19 ==> NC */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
/* H20 : TP41 */
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
/* H21 : XTAL_FREQ_SEL */
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
/* H22 : GPP_H22 ==> NC */
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
/* H23 : GPP_H23_STRAP */
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_OD */
|
||||
PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
|
||||
|
||||
/* SD card detect VGPIO */
|
||||
PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_gpio_table(size_t *num)
|
||||
|
|
@ -205,24 +410,35 @@ const struct pad_config *__weak variant_gpio_table(size_t *num)
|
|||
|
||||
/* GPIOs needed prior to ramstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* H1_SLAVE_SPI_CS_L */
|
||||
/* B15 : H1_SLAVE_SPI_CS_L */
|
||||
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
|
||||
/* H1_SLAVE_SPI_CLK */
|
||||
/* B16 : H1_SLAVE_SPI_CLK */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
|
||||
/* H1_SLAVE_SPI_MISO_R */
|
||||
/* B17 : H1_SLAVE_SPI_MISO_R */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
|
||||
/* H1_SLAVE_SPI_MOSI_R */
|
||||
/* B18 : H1_SLAVE_SPI_MOSI_R */
|
||||
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
|
||||
/* PCH_WP_OD */
|
||||
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
|
||||
/*
|
||||
* H1_PCH_INT_ODL
|
||||
* C21 : H1_PCH_INT_ODL
|
||||
* TODO Configure it back to invert mode, when
|
||||
* ITSS IPCx configuration is fixed in FSP.
|
||||
*/
|
||||
PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE),
|
||||
/* WLAN_PE_RST# */
|
||||
/* C23 : WLAN_PE_RST# */
|
||||
PAD_CFG_GPO(GPP_C23, 1, DEEP),
|
||||
/* F2 : MEM_CH_SEL */
|
||||
PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
|
||||
/* F11 : PCH_MEM_STRAP2 */
|
||||
PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
|
||||
/* F20 : PCH_MEM_STRAP0 */
|
||||
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
|
||||
/* F21 : PCH_MEM_STRAP1 */
|
||||
PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
|
||||
/* F22 : PCH_MEM_STRAP3 */
|
||||
PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
|
||||
|
||||
};
|
||||
|
||||
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
|
||||
|
|
|
|||
Loading…
Reference in New Issue