Re-integrate "USE_OPTION_TABLE" code.

Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/Kconfig

@@ -83,6 +83,7 @@ config CCACHE
 config USE_OPTION_TABLE
 	bool "Use CMOS for configuration values"
 	default n
+	depends on HAVE_OPTION_TABLE
 	help
 	  Enable this option if coreboot shall read options from the "CMOS"
 	  NVRAM instead of using hard coded values.
@@ -189,13 +190,17 @@ config HAVE_MAINBOARD_RESOURCES
 	bool
 	default n
 
+config USE_OPTION_TABLE
+	bool
+	default n
+
 config HAVE_OPTION_TABLE
 	bool
-	default y
+	default n
 	help
 	  This variable specifies whether a given board has a cmos.layout
 	  file containing NVRAM/CMOS bit definitions.
-	  It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
+	  It defaults to 'n' but can be selected in mainboard/*/Kconfig.
 
 config PIRQ_ROUTE
 	bool

src/arch/i386/boot/coreboot_table.c

@@ -29,7 +29,7 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
 #include <option_table.h>
 #endif
 
@@ -188,7 +188,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -535,7 +535,7 @@ unsigned long write_coreboot_table(
 	rom_table_end &= ~0xffff;
 	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
 	{
 		struct lb_record *rec_dest = lb_new_record(head);
 		/* Copy the option config table, it's already a lb_record... */

src/arch/i386/init/bootblock_normal.c

@@ -2,7 +2,7 @@
 
 #include <arch/io.h>
 #include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 static void main(unsigned long bist)
 {

src/cpu/amd/dualcore/dualcore.c

@@ -6,6 +6,7 @@
 #endif
 
 #include "cpu/amd/dualcore/dualcore_id.c"
+#include <pc80/mc146818rtc.h>
 
 static inline unsigned get_core_num_in_bsp(unsigned nodeid)
 {
@@ -56,8 +57,7 @@ static inline void start_other_cores(void)
 	unsigned nodes;
 	unsigned nodeid;
 
-	if (CONFIG_HAVE_OPTION_TABLE &&
-	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0)  {
+	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0))  {
 		return; // disable multi_core
 	}
 

src/cpu/amd/model_10xxx/init_cpus.c

@@ -109,13 +109,12 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	/* get_nodes define in ht_wrapper.c */
 	nodes = get_nodes();
 
-	disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
-	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 mean multi core
+	if (!CONFIG_LOGICAL_CPUS ||
+	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
+	} else {
+		disable_siblings = 0;
 	}
-#endif
 
 	/* Assume that all node are same stepping, otherwise we can use use
 	   nb_cfg_54 from bsp for all nodes */

src/cpu/amd/model_fxx/init_cpus.c

@@ -36,13 +36,12 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
 	/* get_nodes define in in_coherent_ht.c */
 	nodes = get_nodes();
 
-	disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
-	if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 mean multi core
+	if (!CONFIG_LOGICAL_CPUS ||
+	    read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {	// 0 means multi core
 		disable_siblings = 1;
+	} else {
+		disable_siblings = 0;
 	}
-#endif
 
 	/* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */
 	nb_cfg_54 = read_nb_cfg_54();

src/cpu/amd/quadcore/quadcore.c

@@ -18,7 +18,7 @@
  */
 
 #include <console/console.h>
-#include <pc80/mc146818rtc_early.c>
+#include <pc80/mc146818rtc.h>
 #include <northbridge/amd/amdht/ht_wrapper.c>
 
 #ifndef SET_NB_CFG_54

src/include/pc80/mc146818rtc.h

@@ -85,15 +85,48 @@
  * LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined
  * in option_table.h
  */
+#if CONFIG_HAVE_OPTION_TABLE
+#include <option_table.h>
+#endif
 
-#if !defined(ASSEMBLY) && !defined(__PRE_RAM__)
+#ifndef UTIL_BUILD_OPTION_TABLE
+#include <arch/io.h>
+static inline unsigned char cmos_read(unsigned char addr)
+{
+	int offs = 0;
+	if (addr >= 128) {
+		offs = 2;
+		addr -= 128;
+	}
+	outb(addr, RTC_BASE_PORT + offs + 0);
+	return inb(RTC_BASE_PORT + offs + 1);
+}
+
+static inline void cmos_write(unsigned char val, unsigned char addr)
+{
+	int offs = 0;
+	if (addr >= 128) {
+		offs = 2;
+		addr -= 128;
+	}
+	outb(addr, RTC_BASE_PORT + offs + 0);
+	outb(val, RTC_BASE_PORT + offs + 1);
+}
+#endif
+
+#if !defined(__ROMCC__)
 void rtc_init(int invalid);
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
 int get_option(void *dest, const char *name);
+unsigned read_option(unsigned start, unsigned size, unsigned def);
 #else
 static inline int get_option(void *dest __attribute__((unused)),
 	const char *name __attribute__((unused))) { return -2; }
+static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
+	{ return def; }
 #endif
+#else
+#include <pc80/mc146818rtc_early.c>
 #endif
 
 #endif /*  PC80_MC146818RTC_H */

src/mainboard/a-trend/atc-6220/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "ATC-6220"
 	depends on BOARD_A_TREND_ATC_6220
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_A_TREND_ATC_6220
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/a-trend/atc-6240/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "ATC-6240"
 	depends on BOARD_A_TREND_ATC_6240
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_A_TREND_ATC_6240
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/abit/be6-ii_v2_0/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "BE6-II V2.0"
 	depends on BOARD_ABIT_BE6_II_V2_0
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ABIT_BE6_II_V2_0
-
 config IRQ_SLOT_COUNT
 	int
 	default 9

src/mainboard/advantech/pcm-5820/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "PCM-5820"
 	depends on BOARD_ADVANTECH_PCM_5820
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ADVANTECH_PCM_5820
-
 config IRQ_SLOT_COUNT
 	int
 	default 2

src/mainboard/amd/db800/Kconfig

@@ -22,11 +22,6 @@ config MAINBOARD_PART_NUMBER
 	default "DB800"
 	depends on BOARD_AMD_DB800
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_AMD_DB800
-
 config IRQ_SLOT_COUNT
 	int
 	default 4

src/mainboard/amd/dbm690t/Kconfig

@@ -11,6 +11,7 @@ config BOARD_AMD_DBM690T
 	select GENERATE_ACPI_TABLES
 	select GENERATE_MP_TABLE
 	select GENERATE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/dbm690t/romstage.c

@@ -40,8 +40,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/amd/mahogany/Kconfig

@@ -11,6 +11,7 @@ config BOARD_AMD_MAHOGANY
 	select GENERATE_ACPI_TABLES
 	select GENERATE_MP_TABLE
 	select GENERATE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG
 	select LIFT_BSP_APIC_ID

src/mainboard/amd/mahogany/romstage.c

@@ -40,8 +40,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/amd/mahogany_fam10/Kconfig

@@ -8,6 +8,7 @@ config BOARD_AMD_MAHOGANY_FAM10
 	select SUPERIO_ITE_IT8718F
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -45,7 +45,6 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/norwich/Kconfig

@@ -21,11 +21,6 @@ config MAINBOARD_PART_NUMBER
 	default "Norwich"
 	depends on BOARD_AMD_NORWICH
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_AMD_NORWICH
-
 config IRQ_SLOT_COUNT
 	int
 	default 6

src/mainboard/amd/pistachio/Kconfig

@@ -8,6 +8,7 @@ config BOARD_AMD_PISTACHIO
 	select SOUTHBRIDGE_AMD_SB600
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/pistachio/romstage.c

@@ -34,8 +34,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/amd/rumba/Kconfig

@@ -38,11 +38,6 @@ config MAINBOARD_PART_NUMBER
 	default "Rumba"
 	depends on BOARD_AMD_RUMBA
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_AMD_RUMBA
-
 config IRQ_SLOT_COUNT
 	int
 	default 2

src/mainboard/amd/serengeti_cheetah/Kconfig

@@ -9,6 +9,7 @@ config BOARD_AMD_SERENGETI_CHEETAH
 	select SUPERIO_WINBOND_W83627HF
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/serengeti_cheetah/ap_romstage.c

@@ -18,8 +18,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/serial.c"
 #include "./arch/i386/lib/printk_init.c"
 

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -26,8 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/amd/serengeti_cheetah_fam10/Kconfig

@@ -8,6 +8,7 @@ config BOARD_AMD_SERENGETI_CHEETAH_FAM10
 	select SUPERIO_WINBOND_W83627HF
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -45,7 +45,6 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/tilapia_fam10/Kconfig

@@ -8,6 +8,7 @@ config BOARD_AMD_TILAPIA_FAM10
 	select SUPERIO_ITE_IT8718F
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -45,7 +45,6 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/arima/hdama/Kconfig

@@ -8,6 +8,7 @@ config BOARD_ARIMA_HDAMA
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_NSC_PC87360
 	select HAVE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM

src/mainboard/arima/hdama/romstage.c

@@ -5,8 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 

src/mainboard/artecgroup/dbe61/Kconfig

@@ -21,11 +21,6 @@ config MAINBOARD_PART_NUMBER
 	default "DBE61"
 	depends on BOARD_ARTECGROUP_DBE61
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ARTECGROUP_DBE61
-
 config IRQ_SLOT_COUNT
 	int
 	default 3

src/mainboard/asi/mb_5blgp/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "MB-5BLGP"
 	depends on BOARD_ASI_MB_5BLGP
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASI_MB_5BLGP
-
 config IRQ_SLOT_COUNT
 	int
 	default 3

src/mainboard/asi/mb_5blmp/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "MB-5BLMP"
 	depends on BOARD_ASI_MB_5BLMP
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASI_MB_5BLMP
-
 config IRQ_SLOT_COUNT
 	int
 	default 5

src/mainboard/asrock/939a785gmh/Kconfig

@@ -13,6 +13,7 @@ config BOARD_ASROCK_939A785GMH
 	select GENERATE_MP_TABLE
 	select GENERATE_PIRQ_TABLE
 	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG
 	select LIFT_BSP_APIC_ID
 	select USE_PRINTK_IN_CAR

src/mainboard/asrock/939a785gmh/romstage.c

@@ -41,8 +41,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/asus/a8n_e/Kconfig

@@ -7,6 +7,7 @@ config BOARD_ASUS_A8N_E
 	select SOUTHBRIDGE_NVIDIA_CK804
 	select SUPERIO_ITE_IT8712F
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/asus/a8n_e/romstage.c

@@ -38,8 +38,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"

src/mainboard/asus/a8v-e_se/Kconfig

@@ -10,6 +10,7 @@ config BOARD_ASUS_A8V_E_SE
 	select SUPERIO_WINBOND_W83627EHG
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM
+	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512

src/mainboard/asus/a8v-e_se/romstage.c

@@ -44,8 +44,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -49,8 +49,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <arch/romcc_io.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/asus/mew-am/Kconfig

@@ -41,11 +41,6 @@ config MAINBOARD_PART_NUMBER
 	default "MEW-AM"
 	depends on BOARD_ASUS_MEW_AM
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_MEW_AM
-
 config IRQ_SLOT_COUNT
 	int
 	default 8

src/mainboard/asus/mew-vm/Kconfig

@@ -25,6 +25,7 @@ config BOARD_ASUS_MEW_VM
 	select SOUTHBRIDGE_INTEL_I82801AX
 	select SUPERIO_SMSC_LPC47B272
 	select ROMCC
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512

src/mainboard/asus/p2b-d/Kconfig

@@ -42,11 +42,6 @@ config MAINBOARD_PART_NUMBER
 	default "P2B-D"
 	depends on BOARD_ASUS_P2B_D
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P2B_D
-
 config IRQ_SLOT_COUNT
 	int
 	default 6

src/mainboard/asus/p2b-ds/Kconfig

@@ -42,11 +42,6 @@ config MAINBOARD_PART_NUMBER
 	default "P2B-DS"
 	depends on BOARD_ASUS_P2B_DS
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P2B_DS
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/asus/p2b-f/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "P2B-F"
 	depends on BOARD_ASUS_P2B_F
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P2B_F
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/asus/p2b-ls/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "P2B-LS"
 	depends on BOARD_ASUS_P2B_LS
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P2B_LS
-
 config IRQ_SLOT_COUNT
 	int
 	default 8

src/mainboard/asus/p2b/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "P2B"
 	depends on BOARD_ASUS_P2B
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P2B
-
 config IRQ_SLOT_COUNT
 	int
 	default 6

src/mainboard/asus/p3b-f/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "P3B-F"
 	depends on BOARD_ASUS_P3B_F
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ASUS_P3B_F
-
 config IRQ_SLOT_COUNT
 	int
 	default 8

src/mainboard/axus/tc320/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "TC320"
 	depends on BOARD_AXUS_TC320
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_AXUS_TC320
-
 # Soldered NIC, internal USB, no real PCI slots.
 config IRQ_SLOT_COUNT
 	int

src/mainboard/azza/pt-6ibd/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "PT-6IBD"
 	depends on BOARD_AZZA_PT_6IBD
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_AZZA_PT_6IBD
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/bcom/winnet100/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "WinNET100"
 	depends on BOARD_BCOM_WINNET100
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_BCOM_WINNET100
-
 # Soldered NIC, internal USB, no real PCI slots.
 config IRQ_SLOT_COUNT
 	int

src/mainboard/bcom/winnetp680/Kconfig

@@ -6,6 +6,7 @@ config BOARD_BCOM_WINNETP680
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SUPERIO_WINBOND_W83697HF
 	select HAVE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 

src/mainboard/biostar/m6tba/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "M6TBA"
 	depends on BOARD_BIOSTAR_M6TBA
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_BIOSTAR_M6TBA
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/broadcom/blast/Kconfig

@@ -8,6 +8,7 @@ config BOARD_BROADCOM_BLAST
 	select SOUTHBRIDGE_BROADCOM_BCM5785
 	select SUPERIO_NSC_PC87417
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/broadcom/blast/romstage.c

@@ -11,8 +11,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 

src/mainboard/compaq/deskpro_en_sff_p600/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "Deskpro EN SFF P600"
 	depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600
-
 config IRQ_SLOT_COUNT
 	int
 	default 5

src/mainboard/dell/s1850/Kconfig

@@ -8,6 +8,7 @@ config BOARD_DELL_S1850
 	select SUPERIO_NSC_PC8374
 	select ROMCC
 	select HAVE_HARD_RESET
+	select HAVE_OPTION_TABLE
 	select BOARD_HAS_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/dell/s1850/romstage.c

@@ -5,8 +5,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"

src/mainboard/digitallogic/adl855pc/Kconfig

@@ -5,6 +5,7 @@ config BOARD_DIGITALLOGIC_ADL855PC
 	select NORTHBRIDGE_INTEL_I855
 	select SOUTHBRIDGE_INTEL_I82801DX
 	select SUPERIO_WINBOND_W83627HF
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -4,10 +4,9 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-//#include "option_table.h"
 #include <stdlib.h>
 #include "pc80/udelay_io.c"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"

src/mainboard/digitallogic/msm586seg/Kconfig

@@ -3,6 +3,7 @@ config BOARD_DIGITALLOGIC_MSM586SEG
 	select ARCH_X86
 	select CPU_AMD_SC520
 	select HAVE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select ROMCC
 

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -4,7 +4,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"

src/mainboard/digitallogic/msm800sev/Kconfig

@@ -22,11 +22,6 @@ config MAINBOARD_PART_NUMBER
 	default "MSM800SEV"
 	depends on BOARD_DIGITALLOGIC_MSM800SEV
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_DIGITALLOGIC_MSM800SEV
-
 config IRQ_SLOT_COUNT
 	int
 	default 9

src/mainboard/eaglelion/5bcm/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "5BCM"
 	depends on BOARD_EAGLELION_5BCM
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_EAGLELION_5BCM
-
 config IRQ_SLOT_COUNT
 	int
 	default 2

src/mainboard/ecs/p6iwp-fe/Kconfig

@@ -42,11 +42,6 @@ config MAINBOARD_PART_NUMBER
 	default "P6IWP-FE"
 	depends on BOARD_ECS_P6IWP_FE
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_ECS_P6IWP_FE
-
 config IRQ_SLOT_COUNT
 	int
 	default 10

src/mainboard/emulation/qemu-x86/Kconfig

@@ -3,6 +3,7 @@ config BOARD_EMULATION_QEMU_X86
 	select ARCH_X86
 	select SOUTHBRIDGE_INTEL_I82371EB
 	select ROMCC
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 	select WARNINGS_ARE_ERRORS

src/mainboard/emulation/qemu-x86/romstage.c

@@ -5,8 +5,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"

src/mainboard/getac/p470/Kconfig

@@ -31,6 +31,7 @@ config BOARD_GETAC_P470
 	select GENERATE_ACPI_TABLES
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
+	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_SLIC

src/mainboard/getac/p470/romstage.c

@@ -31,8 +31,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>

src/mainboard/gigabyte/ga-6bxc/Kconfig

@@ -39,11 +39,6 @@ config MAINBOARD_PART_NUMBER
 	default "GA-6BXC"
 	depends on BOARD_GIGABYTE_GA_6BXC
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_GIGABYTE_GA_6BXC
-
 config IRQ_SLOT_COUNT
 	int
 	default 6

src/mainboard/gigabyte/ga-6bxe/Kconfig

@@ -41,11 +41,6 @@ config MAINBOARD_PART_NUMBER
 	default "GA-6BXE"
 	depends on BOARD_GIGABYTE_GA_6BXE
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_GIGABYTE_GA_6BXE
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/gigabyte/ga_2761gxdk/Kconfig

@@ -7,6 +7,7 @@ config BOARD_GIGABYTE_GA_2761GXDK
 	select SOUTHBRIDGE_SIS_SIS966
 	select SUPERIO_ITE_IT8716F
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select USE_PRINTK_IN_CAR
 	select USE_DCACHE_RAM

src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c

@@ -41,8 +41,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/serial.c"
 
 #include "lib/uart8250.c"

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -50,8 +50,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #if CONFIG_USBDEBUG

src/mainboard/gigabyte/m57sli/Kconfig

@@ -8,6 +8,7 @@ config BOARD_GIGABYTE_M57SLI
 	select SUPERIO_ITE_IT8716F
 	select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/gigabyte/m57sli/ap_romstage.c

@@ -39,8 +39,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/serial.c"
 
 #include "lib/uart8250.c"

src/mainboard/gigabyte/m57sli/romstage.c

@@ -48,8 +48,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #if CONFIG_USBDEBUG

src/mainboard/hp/dl145_g3/Kconfig

@@ -8,6 +8,7 @@ config BOARD_HP_DL145_G3
 	select SOUTHBRIDGE_BROADCOM_BCM5785
 	select SUPERIO_NSC_PC87417
 	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/hp/dl145_g3/romstage.c

@@ -54,8 +54,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include "lib/ramtest.c"

src/mainboard/hp/e_vectra_p2706t/Kconfig

@@ -44,11 +44,6 @@ config MAINBOARD_PART_NUMBER
 	default "e-Vectra P2706T"
 	depends on BOARD_HP_E_VECTRA_P2706T
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_HP_E_VECTRA_P2706T
-
 config IRQ_SLOT_COUNT
 	int
 	default 3

src/mainboard/ibase/mb899/Kconfig

@@ -11,6 +11,7 @@ config BOARD_IBASE_MB899
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_HARD_RESET
+	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_MAINBOARD_RESOURCES
 	select MMCONF_SUPPORT

src/mainboard/ibase/mb899/romstage.c

@@ -34,8 +34,7 @@
 
 #include "superio/winbond/w83627ehg/w83627ehg.h"
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>

src/mainboard/ibm/e325/Kconfig

@@ -7,6 +7,7 @@ config BOARD_IBM_E325
 	select SOUTHBRIDGE_AMD_AMD8111
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_NSC_PC87366
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/ibm/e325/romstage.c

@@ -7,8 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 

src/mainboard/ibm/e326/Kconfig

@@ -7,6 +7,7 @@ config BOARD_IBM_E326
 	select SOUTHBRIDGE_AMD_AMD8111
 	select SOUTHBRIDGE_AMD_AMD8131
 	select SUPERIO_NSC_PC87366
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select USE_PRINTK_IN_CAR

src/mainboard/ibm/e326/romstage.c

@@ -7,8 +7,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 

src/mainboard/iei/pcisa-lx-800-r10/Kconfig

@@ -21,11 +21,6 @@ config MAINBOARD_PART_NUMBER
 	default "PCISA-LX-800-R10"
 	depends on BOARD_IEI_PCISA_LX_800_R10
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_IEI_PCISA_LX_800_R10
-
 config IRQ_SLOT_COUNT
 	int
 	default 9

src/mainboard/intel/d810e2cb/Kconfig

@@ -40,11 +40,6 @@ config MAINBOARD_PART_NUMBER
 	default "D810E2CB"
 	depends on BOARD_INTEL_D810E2CB
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_INTEL_D810E2CB
-
 config IRQ_SLOT_COUNT
 	int
 	default 7

src/mainboard/intel/d945gclf/Kconfig

@@ -29,6 +29,7 @@ config BOARD_INTEL_D945GCLF
 	select GENERATE_ACPI_TABLES
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
+	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/intel/d945gclf/romstage.c

@@ -33,8 +33,7 @@
 
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>

src/mainboard/intel/eagleheights/Kconfig

@@ -6,6 +6,7 @@ config BOARD_INTEL_EAGLEHEIGHTS
 	select SOUTHBRIDGE_INTEL_I3100
 	select SUPERIO_INTEL_I3100
 	select SUPERIO_SMSC_SMSCSUPERIO
+	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_HAS_HARD_RESET
 	select BOARD_HAS_FADT

src/mainboard/intel/eagleheights/romstage.c

@@ -29,8 +29,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>

src/mainboard/intel/jarrell/Kconfig

@@ -9,6 +9,7 @@ config BOARD_INTEL_JARRELL
 	select ROMCC
 	select HAVE_HARD_RESET
 	select BOARD_HAS_HARD_RESET
+	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select UDELAY_TSC

src/mainboard/intel/jarrell/romstage.c

@@ -5,8 +5,7 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"

src/mainboard/intel/mtarvon/Kconfig

@@ -22,11 +22,6 @@ config MAINBOARD_PART_NUMBER
 	default "3100 devkit (Mt. Arvon)"
 	depends on BOARD_INTEL_MTARVON
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_INTEL_MTARVON
-
 config IRQ_SLOT_COUNT
 	int
 	default 1

src/mainboard/intel/mtarvon/romstage.c

@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"

src/mainboard/intel/truxton/Kconfig

@@ -23,11 +23,6 @@ config MAINBOARD_PART_NUMBER
 	default "Truxton"
 	depends on BOARD_INTEL_TRUXTON
 
-config HAVE_OPTION_TABLE
-	bool
-	default n
-	depends on BOARD_INTEL_TRUXTON
-
 config IRQ_SLOT_COUNT
 	int
 	default 1

src/mainboard/intel/truxton/romstage.c

@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
 #include "lib/ramtest.c"