mb/*: Use common IPMI KCS driver
Remove duplicated code and instead use the IPMI KCS driver, which provides the same functionality. Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
This commit is contained in:
Patrick Rudolph
Patrick Rudolph
parent
a96c4a1340
commit
eb50d9a4fe
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@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS
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select DRIVERS_ASPEED_AST2050
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
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select IPMI_KCS
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config MAINBOARD_DIR
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string
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@ -217,7 +217,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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chip drivers/generic/generic # BMC KCS
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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end
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end
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@ -53,9 +53,6 @@ DefinitionBlock (
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#include <southbridge/amd/common/acpi/sleepstates.asl>
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/* IPMI KCS enable */
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Name (KCSE, 0x1)
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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@ -489,13 +486,6 @@ DefinitionBlock (
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Name (_HID, EisaId ("PNP0A05"))
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Name (_ADR, 0x00140003)
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OperationRegion (BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */
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Field (BMRG, AnyAcc, NoLock, Preserve)
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{
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BMRI, 8, /* Index */
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BMRD, 8, /* Data */
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}
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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@ -617,27 +607,6 @@ DefinitionBlock (
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})
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}
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}
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Device (KCS1) { /* IPMI KCS */
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Name (_HID, EISAID ("IPI0001")) /* ASpeed BMC */
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Method (_STA, 0, NotSerialized) {
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If (KCSE) { /* Detection enabled */
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If (LNotEqual (BMRD, 0xff)) {
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Return (0x0f) /* Device present */
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}
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Return (Zero)
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}
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Return (Zero)
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}
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Method (_CRS, 0) {
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Return (ResourceTemplate() {
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IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02)
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})
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}
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Method (_IFT, 0, NotSerialized) { /* Interface type */
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Return (One) /* KCS interface */
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}
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}
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}
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/* High Precision Event Timer */
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@ -47,7 +47,6 @@ void set_pcie_dereset(void)
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* enable the dedicated function in kgpe-d16 board.
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* This function is called earlier than sr5650_enable.
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*************************************************/
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#define BMC_KCS_BASE 0xca2
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static void mainboard_enable(struct device *dev)
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{
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@ -69,13 +68,6 @@ static void mainboard_enable(struct device *dev)
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set_pcie_dereset();
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/* get_ide_dma66(); */
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/* Enable access to the BMC IPMI via KCS */
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struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0);
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struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE);
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res->base = BMC_KCS_BASE;
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res->size = 1;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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/* override the default SATA PHY setup */
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@ -11,8 +11,9 @@ chip soc/intel/fsp_broadwell_de
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip drivers/generic/generic # BMC KCS
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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end
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end # LPC Bridge
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device pci 1f.2 on end # SATA Controller
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@ -27,9 +27,6 @@ DefinitionBlock(
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{
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#include "acpi/platform.asl"
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Name (IDTP, 0x0CA2)
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Name (ICDP, 0x0CA6)
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Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
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Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
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@ -293,97 +290,5 @@ DefinitionBlock(
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}
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}
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Scope (_SB.PCI0.LPC0)
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{
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Device (SPMI)
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{
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Name (_HID, EisaId ("IPI0001"))
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Name (_STR, Unicode ("IPMI_KCS"))
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Name (_UID, 0x00)
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OperationRegion (IPST, SystemIO, ICDP, 0x01)
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Field (IPST, ByteAcc, NoLock, Preserve)
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{
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STAS, 8
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}
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Method (_STA, 0, NotSerialized) {
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Return (0x0f)
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}
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Name (ICRS, ResourceTemplate ()
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{
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IO (Decode16,
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0x0000,
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0x0000,
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0x00,
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0x00,
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_Y01)
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IO (Decode16,
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0x0000,
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0x0000,
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0x00,
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0x00,
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_Y02)
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})
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Method (_CRS, 0, NotSerialized)
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{
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH)
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CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB)
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CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH)
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CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL)
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IPDB = IDTP
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IPDH = IDTP
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IPDL = 0x01
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IPCB = ICDP
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IPCH = ICDP
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IPCL = 0x01
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Return (ICRS)
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}
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Method (_IFT, 0, NotSerialized) {
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Return (0x01)
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}
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Method(_SRV, 0, NotSerialized) {
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Return (0x0200)
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}
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}
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Device (SYSR)
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{
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Name (_HID, EisaId ("PNP0C02"))
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Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
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{
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IO (Decode16,
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0x0CA2,
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0x0CA2,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CA6,
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0x0CA6,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CA8,
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0x0CA8,
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0x01,
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0x01,
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)
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IO (Decode16,
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0x0CAC,
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0x0CAC,
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0x01,
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0x01,
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)
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})
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}
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}
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#include "acpi/mainboard.asl"
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}
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@ -15,55 +15,17 @@
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*/
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#include <device/device.h>
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#include <smbios.h>
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#if CONFIG(VGA_ROM_RUN)
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#include <x86emu/x86emu.h>
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#endif
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#include <pc80/mc146818rtc.h>
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#include <cf9_reset.h>
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#include "ipmi.h"
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#define BMC_KCS_BASE 0xca2
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#define INTERFACE_IS_IO 0x1
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#if CONFIG(GENERATE_SMBIOS_TABLES)
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static int mainboard_smbios_data(struct device *dev, int *handle,
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unsigned long *current)
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{
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int len = 0;
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// add IPMI Device Information
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len += smbios_write_type38(
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current, handle,
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SMBIOS_BMC_INTERFACE_KCS,
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0x20, // IPMI Version
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0x20, // I2C address
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0xff, // no NV storage
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BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address
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0x40,
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0); // no IRQ
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return len;
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}
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#endif
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/*
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* mainboard_enable is executed as first thing after enumerate_buses().
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* This is the earliest point to add customization.
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*/
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static void mainboard_enable(struct device *dev)
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{
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#if CONFIG(GENERATE_SMBIOS_TABLES)
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dev->ops->get_smbios_data = mainboard_smbios_data;
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#endif
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/* Enable access to the BMC IPMI via KCS */
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struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0);
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struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE);
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ipmi_oem_rsp_t rsp;
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res->base = BMC_KCS_BASE;
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res->size = 1;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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if (is_ipmi_clear_cmos_set(&rsp)) {
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/* TODO: Should also try to restore CMOS to cmos.default
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