soc/amd/glinda: Use common fsp-s preloader
Use the common preloader for fsp-s Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -72,6 +72,7 @@ config SOC_AMD_GLINDA
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
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select SSE2
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select SSE2
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select UDK_2017_BINDING
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select UDK_2017_BINDING
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select USE_DDR5
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select USE_DDR5
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@ -40,7 +40,6 @@ ramstage-y += fsp_s_params.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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ramstage-y += mca.c
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ramstage-y += mca.c
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ramstage-y += preload.c
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ramstage-y += reset.c
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ramstage-y += reset.c
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ramstage-y += root_complex.c
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ramstage-y += root_complex.c
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ramstage-y += uart.c
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ramstage-y += uart.c
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@ -1,13 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Move to common? */
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#include <bootstate.h>
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#include <fsp/api.h>
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static void start_fsps_preload(void *unused)
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{
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preload_fsps();
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);
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