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intel car: Unify whitespace and comment fixes 

Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15759
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-20 12:50:20 +03:00
parent 9ec691429f
commit eb61ea84f7
5 changed files with 15 additions and 16 deletions
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2
src/cpu/intel/car/cache_as_ram_ht.inc
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@ -288,7 +288,7 @@ no_msr_11e:
invd invd
movl %eax, %cr0 movl %eax, %cr0
/* Clear the cache memory reagion. */ /* Clear the cache memory region. This will also fill up the cache. */
cld cld
xorl %eax, %eax xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi movl $CACHE_AS_RAM_BASE, %edi

5
src/cpu/intel/haswell/cache_as_ram.inc
View File

@ -30,8 +30,7 @@
#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) #define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
#define NoEvictMod_MSR 0x2e0 #define NoEvictMod_MSR 0x2e0
@ -108,7 +107,7 @@ clear_mtrrs:
andl $~2, %eax andl $~2, %eax
wrmsr wrmsr
/* Clear the cache memory region. This will also fill up the cache */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $(CACHE_AS_RAM_SIZE >> 2), %ecx

2
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@ -113,7 +113,7 @@ clear_var_mtrrs:
andl $~2, %eax andl $~2, %eax
wrmsr wrmsr
/* Clear the cache memory region. This will also fill up the cache */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $(CACHE_AS_RAM_SIZE >> 2), %ecx

2
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -105,7 +105,7 @@ clear_mtrrs:
andl $~2, %eax andl $~2, %eax
wrmsr wrmsr
/* Clear the cache memory region. This will also fill up the cache */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $(CACHE_AS_RAM_SIZE >> 2), %ecx

2
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -83,7 +83,7 @@ clear_mtrrs:
invd invd
movl %eax, %cr0 movl %eax, %cr0
/* Clear the cache memory reagion. */ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $(CACHE_AS_RAM_SIZE >> 2), %ecx