src: Use include <reset.h> when appropriate

Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/arch/x86/cf9_reset.c

@@ -18,7 +18,6 @@
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <halt.h>
-#include <reset.h>
 
 /*
  * A system reset in terms of the CF9 register asserts the INIT#

src/cpu/amd/family_10h-family_15h/init_cpus.h

@@ -22,7 +22,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/amd/multicore.h>
-#include <reset.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include "defaults.h"
 

src/cpu/intel/fsp_model_406dx/bootblock.c

@@ -21,7 +21,6 @@
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
-#include <reset.h>
 #include <southbridge/intel/fsp_rangeley/soc.h>
 
 #include "model_406dx.h"

src/drivers/intel/fsp2_0/stage_cache.c

@@ -17,7 +17,6 @@
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <stage_cache.h>
-#include <reset.h>
 #include <program_loading.h>
 
 void stage_cache_external_region(void **base, size_t *size)

src/ec/google/chromeec/ec.c

@@ -23,7 +23,6 @@
 #include <bootstate.h>
 #include <delay.h>
 #include <elog.h>
-#include <reset.h>
 #include <rtc.h>
 #include <stdlib.h>
 #include <security/vboot/vboot_common.h>

src/lib/hardwaremain.c

@@ -29,7 +29,6 @@
 #include <device/pci.h>
 #include <delay.h>
 #include <stdlib.h>
-#include <reset.h>
 #include <boot/tables.h>
 #include <program_loading.h>
 #if CONFIG(HAVE_ACPI_RESUME)

src/mainboard/google/foster/pmic.c

@@ -18,11 +18,11 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/i2c_simple.h>
+#include <reset.h>
 #include <stdint.h>
 #include <stdlib.h>
 
 #include "pmic.h"
-#include "reset.h"
 
 enum {
 	MAX77620_I2C_ADDR = 0x3c

src/mainboard/google/smaug/pmic.c

@@ -18,11 +18,11 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/i2c_simple.h>
+#include <reset.h>
 #include <stdint.h>
 #include <stdlib.h>
 
 #include "pmic.h"
-#include "reset.h"
 
 enum {
 	MAX77620_I2C_ADDR = 0x3c,

src/mainboard/google/veyron/bootblock.c

@@ -18,7 +18,6 @@
 #include <assert.h>
 #include <bootblock_common.h>
 #include <delay.h>
-#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>

src/mainboard/google/veyron_mickey/bootblock.c

@@ -18,7 +18,6 @@
 #include <assert.h>
 #include <bootblock_common.h>
 #include <delay.h>
-#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>

src/mainboard/google/veyron_rialto/bootblock.c

@@ -18,7 +18,6 @@
 #include <assert.h>
 #include <bootblock_common.h>
 #include <delay.h>
-#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>

src/security/tpm/tspi/tspi.c

@@ -17,7 +17,6 @@
 
 #include <console/cbmem_console.h>
 #include <console/console.h>
-#include <reset.h>
 #include <security/tpm/tspi.h>
 #include <security/tpm/tss.h>
 #include <stdlib.h>

src/security/vboot/common.c

@@ -16,7 +16,6 @@
 #include <assert.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <reset.h>
 #include <stdint.h>
 #include <string.h>
 #include <symbols.h>

src/soc/cavium/common/bdk-coreboot.c

@@ -22,7 +22,6 @@
 #include <device/i2c_simple.h>
 #include <endian.h>
 #include <delay.h>
-#include <reset.h>
 #include <soc/timer.h>
 
 // BDK

src/soc/intel/braswell/romstage/romstage.c

@@ -31,7 +31,6 @@
 #include <mrc_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <reset.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <fsp/util.h>
 #include <soc/gpio.h>

src/soc/intel/common/block/cpu/cpulib.c

@@ -24,7 +24,6 @@
 #include <delay.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
-#include <reset.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>

src/soc/intel/fsp_baytrail/bootblock/bootblock.c

@@ -27,7 +27,6 @@
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/gpio.h>
-#include <reset.h>
 
 /*
  * check for a warm reset and do a hard reset instead.

src/soc/intel/skylake/romstage/romstage.c

@@ -26,7 +26,6 @@
 #include <elog.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/pmclib.h>
-#include <reset.h>
 #include <soc/pci_devs.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>

src/southbridge/amd/agesa/hudson/early_setup.c

@@ -20,7 +20,7 @@
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
-#include <reset.h>
+
 #include "hudson.h"
 
 void hudson_pci_port80(void)

src/southbridge/amd/pi/hudson/early_setup.c

@@ -22,7 +22,7 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
-#include <reset.h>
+
 #include "hudson.h"
 #include "pci_devs.h"
 #include <Fch/Fch.h>

src/southbridge/amd/sb700/early_setup.c

@@ -25,7 +25,6 @@
 #include <cpu/x86/msr.h>
 #include <device/pci.h>
 
-#include <reset.h>
 #include "sb700.h"
 #include "smbus.h"
 

src/southbridge/nvidia/ck804/early_setup_car.c

@@ -17,7 +17,9 @@
  */
 
 #include <arch/io.h>
+#include <reset.h>
 #include <southbridge/amd/common/reset.h>
+
 #include "ck804.h"
 
 /* Someone messed up and snuck in some K8-specific code */